| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_llvm_gs.c | 568 unsigned num_sgprs, num_vgprs; in si_llvm_build_gs_prolog() local
577 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR; in si_llvm_build_gs_prolog()
579 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR; in si_llvm_build_gs_prolog()
582 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2; in si_llvm_build_gs_prolog()
586 for (unsigned i = 0; i < num_sgprs; ++i) { in si_llvm_build_gs_prolog()
593 returns[num_sgprs + i] = ctx->ac.f32; in si_llvm_build_gs_prolog()
597 si_llvm_create_func(ctx, "gs_prolog", returns, num_sgprs + num_vgprs, 0); in si_llvm_build_gs_prolog()
611 for (unsigned i = 0; i < num_sgprs; i++) { in si_llvm_build_gs_prolog()
616 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i); in si_llvm_build_gs_prolog()
618 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, ""); in si_llvm_build_gs_prolog()
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| D | si_shader_llvm.c | 471 unsigned num_sgprs, num_vgprs; in si_build_wrapper_function() local
486 num_sgprs = 0; in si_build_wrapper_function()
497 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4; in si_build_wrapper_function()
504 while (gprs < num_sgprs + num_vgprs) { in si_build_wrapper_function()
531 ac_add_arg(&ctx->args, gprs < num_sgprs ? AC_ARG_SGPR : AC_ARG_VGPR, size, arg_type, NULL); in si_build_wrapper_function()
533 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs)); in si_build_wrapper_function()
534 assert(gprs + size <= num_sgprs + num_vgprs && in si_build_wrapper_function()
535 (gprs >= num_sgprs || gprs + size <= num_sgprs)); in si_build_wrapper_function()
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| D | si_shader.c | 706 unsigned num_sgprs = shader->selector->info.base.image_buffers & (1 << i) ? 4 : 8; in si_create_function() local
708 while (ctx->args.num_sgprs_used % num_sgprs != 0) in si_create_function()
711 ac_add_arg(&ctx->args, AC_ARG_SGPR, num_sgprs, AC_ARG_INT, &ctx->cs_image[i]); in si_create_function()
1003 if (conf->num_sgprs) { in si_calculate_max_simd_waves()
1005 MIN2(max_simd_waves, sscreen->info.num_physical_sgprs_per_simd / conf->num_sgprs); in si_calculate_max_simd_waves()
1035 conf->num_sgprs, conf->num_vgprs, si_get_shader_binary_size(screen, shader), in si_shader_dump_stats_for_shader_db()
1066 conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, in si_shader_dump_stats()
1946 if (shader->config.num_sgprs > max_sgprs || shader->config.num_vgprs > max_vgprs) { in si_compile_shader()
1950 shader->config.num_sgprs, shader->config.num_vgprs, max_sgprs, max_vgprs); in si_compile_shader()
2433 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs); in si_fix_resource_usage()
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| D | si_compute.c | 99 out_config->num_sgprs = code_object->wavefront_sgpr_count; in code_object_to_config()
154 unsigned num_sgprs = sel->info.base.image_buffers & (1 << i) ? 4 : 8; in si_create_compute_state_async() local
156 if (align(user_sgprs, num_sgprs) + num_sgprs > 16) in si_create_compute_state_async()
159 user_sgprs = align(user_sgprs, num_sgprs); in si_create_compute_state_async()
162 user_sgprs += num_sgprs; in si_create_compute_state_async()
200 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); in si_create_compute_state_async()
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| D | si_state_shaders.c | 498 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_ls()
546 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) in si_shader_hs()
617 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_es()
882 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_gs()
912 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) | in si_shader_gs()
1471 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_vs()
1682 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_ps()
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| D | si_descriptors.c | 2133 unsigned num_sgprs = 8; in si_emit_compute_shader_pointers() local
2138 num_sgprs = 4; in si_emit_compute_shader_pointers()
2141 radeon_emit_array(cs, &desc->list[desc_offset], num_sgprs); in si_emit_compute_shader_pointers()
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| D | si_compute_prim_discard.c | 1381 S_00B848_SGPRS(sctx->chip_class <= GFX9 ? (shader->config.num_sgprs - 1) / 8 : 0) | in si_dispatch_prim_discard_cs_and_draw()
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| /external/mesa3d/src/amd/common/ |
| D | ac_binary.c | 59 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8); in ac_parse_shader_binary_config()
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| D | ac_binary.h | 38 unsigned num_sgprs; member
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| D | ac_rtld.c | 526 config->num_sgprs = MAX2(config->num_sgprs, c.num_sgprs); in ac_rtld_read_config()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_shader_args.c | 35 uint8_t num_sgprs) in set_loc() argument
38 ud_info->num_sgprs = num_sgprs; in set_loc()
39 *sgpr_idx += num_sgprs; in set_loc()
44 uint8_t num_sgprs) in set_loc_shader() argument
50 set_loc(ud_info, sgpr_idx, num_sgprs); in set_loc_shader()
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| D | radv_shader.c | 881 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3); in radv_postprocess_config() local
891 config_out->num_sgprs = num_sgprs; in radv_postprocess_config()
921 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8); in radv_postprocess_config()
1547 if (conf->num_sgprs) { in radv_get_max_waves()
1548 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8); in radv_get_max_waves()
1617 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs; in radv_GetShaderInfoAMD()
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| D | radv_shader.h | 198 uint8_t num_sgprs; member
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| D | radv_cmd_buffer.c | 714 assert(loc->num_sgprs == 1); in radv_emit_userdata_address()
944 assert(loc->num_sgprs == count); in radv_emit_inline_push_consts()
5701 assert(loc->num_sgprs == 3); in radv_emit_dispatch_packets()
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| D | radv_pipeline.c | 5696 s->value.u64 = shader->config.num_sgprs; in radv_GetPipelineExecutableStatisticsKHR()
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_validate.cpp | 275 unsigned num_sgprs = 0; in validate_ir() local
308 if (num_sgprs < 2) in validate_ir()
309 sgpr[num_sgprs++] = op.tempId(); in validate_ir()
316 …check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", i… in validate_ir()
728 ….type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() … in validate_ra()
749 …ype() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg()… in validate_ra()
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| D | aco_optimizer.cpp | 692 unsigned num_sgprs = 0; in check_vop3_operands() local
701 if (num_sgprs < 2) in check_vop3_operands()
702 sgpr[num_sgprs++] = op.tempId(); in check_vop3_operands()
1672 unsigned num_sgprs = (op[0].type() == RegType::sgpr) + (op[1].type() == RegType::sgpr); in combine_ordering_test() local
1673 if (num_sgprs > (ctx.program->chip_class >= GFX10 ? 2 : 1)) in combine_ordering_test()
1694 if (neg[0] || neg[1] || abs[0] || abs[1] || opsel || num_sgprs > 1) { in combine_ordering_test()
2478 unsigned num_sgprs = !!sgpr_ids[0] + !!sgpr_ids[1]; in apply_sgprs() local
2499 if (num_sgprs && ctx.uses[sgpr_info_id] > 1 && !instr->isVOP3() && !instr->isSDWA()) in apply_sgprs()
2504 if (new_sgpr && num_sgprs >= max_sgprs) in apply_sgprs()
2523 sgpr_ids[num_sgprs++] = sgpr.id(); in apply_sgprs()
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| D | aco_register_allocation.cpp | 2481 program->config->num_sgprs = get_sgpr_alloc(program, program->sgpr_limit); in register_allocation()
2483 program->config->num_sgprs = align(ctx.max_used_sgpr + 1 + get_extra_sgprs(program), 8); in register_allocation()
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