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Searched refs:num_vgprs (Results 1 – 16 of 16) sorted by relevance

/external/mesa3d/src/amd/common/
Dac_binary.c55 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8); in ac_parse_shader_binary_config()
57 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4); in ac_parse_shader_binary_config()
136 conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8); in ac_parse_shader_binary_config()
Dac_binary.h39 unsigned num_vgprs; member
Dac_rtld.c527 config->num_vgprs = MAX2(config->num_vgprs, c.num_vgprs); in ac_rtld_read_config()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader.c549 unsigned num_user_sgprs, num_vgprs; in si_create_function() local
571 num_vgprs = ngg_cull_shader ? 9 : 5; in si_create_function()
576 for (i = 0; i < num_vgprs; i++) in si_create_function()
1008 if (conf->num_vgprs) { in si_calculate_max_simd_waves()
1012 max_simd_waves = MIN2(max_simd_waves, max_vgprs / conf->num_vgprs); in si_calculate_max_simd_waves()
1035 conf->num_sgprs, conf->num_vgprs, si_get_shader_binary_size(screen, shader), in si_shader_dump_stats_for_shader_db()
1066 conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, in si_shader_dump_stats()
1946 if (shader->config.num_sgprs > max_sgprs || shader->config.num_vgprs > max_vgprs) { in si_compile_shader()
1950 shader->config.num_sgprs, shader->config.num_vgprs, max_sgprs, max_vgprs); in si_compile_shader()
2518 shader->config.num_vgprs = MAX2(shader->config.num_vgprs, shader->info.num_input_vgprs); in si_create_shader_variant()
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Dsi_shader_llvm.c471 unsigned num_sgprs, num_vgprs; in si_build_wrapper_function() local
487 num_vgprs = 0; in si_build_wrapper_function()
496 assert(num_vgprs == 0); in si_build_wrapper_function()
499 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4; in si_build_wrapper_function()
504 while (gprs < num_sgprs + num_vgprs) { in si_build_wrapper_function()
534 assert(gprs + size <= num_sgprs + num_vgprs && in si_build_wrapper_function()
Dsi_shader_llvm_gs.c568 unsigned num_sgprs, num_vgprs; in si_llvm_build_gs_prolog() local
580 num_vgprs = 5; /* ES inputs are not needed by GS */ in si_llvm_build_gs_prolog()
583 num_vgprs = 8; in si_llvm_build_gs_prolog()
591 for (unsigned i = 0; i < num_vgprs; ++i) { in si_llvm_build_gs_prolog()
597 si_llvm_create_func(ctx, "gs_prolog", returns, num_sgprs + num_vgprs, 0); in si_llvm_build_gs_prolog()
615 for (unsigned i = 0; i < num_vgprs; i++) { in si_llvm_build_gs_prolog()
Dsi_state_shaders.c497 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_ls()
545 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) | in si_shader_hs()
616 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_es()
868 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | in si_shader_gs()
911 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_gs()
1148 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) | in gfx10_shader_ngg()
1458 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) | in si_shader_vs()
1677 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) | in si_shader_ps()
Dsi_compute.c100 out_config->num_vgprs = code_object->workitem_vgpr_count; in code_object_to_config()
192 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) / in si_create_compute_state_async()
Dsi_compute_prim_discard.c1372 assert(shader->config.num_vgprs * WAVES_PER_TG <= 256 * 4); in si_dispatch_prim_discard_cs_and_draw()
1380 cs, S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_dispatch_prim_discard_cs_and_draw()
Dgfx10_shader_ngg.c1179 unsigned num_vgprs = uses_tes_prim_id ? 4 : 3; in gfx10_emit_ngg_culling_epilogue() local
1180 for (unsigned i = 0; i < num_vgprs; i++) { in gfx10_emit_ngg_culling_epilogue()
1184 if (num_vgprs == 3) in gfx10_emit_ngg_culling_epilogue()
/external/mesa3d/src/amd/vulkan/
Dradv_shader.c879 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs); in radv_postprocess_config() local
890 config_out->num_vgprs = num_vgprs; in radv_postprocess_config()
913 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / in radv_postprocess_config()
1555 if (conf->num_vgprs) { in radv_get_max_waves()
1556 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4); in radv_get_max_waves()
1616 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs; in radv_GetShaderInfoAMD()
Dradv_pipeline.c249 (256 / pipeline->shaders[i]->config.num_vgprs)); in radv_pipeline_init_scratch()
5704 s->value.u64 = shader->config.num_vgprs; in radv_GetPipelineExecutableStatisticsKHR()
/external/mesa3d/src/amd/compiler/
Daco_validate.cpp727 …() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) || in validate_ra()
748 … == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) || in validate_ra()
Daco_register_allocation.cpp2479 program->config->num_vgprs = align(ctx.max_used_vgpr + 1, 4); in register_allocation()
Daco_lower_to_hw_instr.cpp821 unsigned shared_vgpr_reg_0 = align(program->config->num_vgprs, 4) + 256; in emit_gfx10_wave64_bpermute()
/external/mesa3d/docs/relnotes/
D20.2.0.rst3300 - ac: align num_vgprs for gfx10.3