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Searched refs:off32 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Dldst-regoffset.ll12 define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize {
15 %addr8_sxtw = getelementptr i8, i8* %base, i32 %off32
28 %offset_uxtw = zext i32 %off32 to i64
40 define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
43 %addr8_sxtwN = getelementptr i16, i16* %base, i32 %off32
56 %offset_uxtw = zext i32 %off32 to i64
65 %offset_sxtw = sext i32 %off32 to i64
83 %offset_uxtwN = zext i32 %off32 to i64
94 define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
97 %addr_sxtwN = getelementptr i32, i32* %base, i32 %off32
[all …]
Darm64-atomic.ll158 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
164 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
183 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
189 %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
208 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
214 %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
233 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
239 %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
266 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) #0 {
272 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
[all …]
Darm64-register-offset-addressing.ll19 %off32.sext.tmp = shl i64 %offset, 32
20 %off32.sext = ashr i64 %off32.sext.tmp, 32
21 %addr8_sxtw = getelementptr i8, i8* %base, i64 %off32.sext
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dldst-regoffset.ll12 define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize {
15 %addr8_sxtw = getelementptr i8, i8* %base, i32 %off32
28 %offset_uxtw = zext i32 %off32 to i64
40 define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize {
43 %addr8_sxtwN = getelementptr i16, i16* %base, i32 %off32
56 %offset_uxtw = zext i32 %off32 to i64
65 %offset_sxtw = sext i32 %off32 to i64
83 %offset_uxtwN = zext i32 %off32 to i64
94 define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize {
97 %addr_sxtwN = getelementptr i32, i32* %base, i32 %off32
[all …]
Darm64-atomic.ll167 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
173 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
192 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
198 %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
217 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
223 %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
242 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
248 %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
275 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) #0 {
281 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
[all …]
Darm64-register-offset-addressing.ll18 %off32.sext.tmp = shl i64 %offset, 32
19 %off32.sext = ashr i64 %off32.sext.tmp, 32
20 %addr8_sxtw = getelementptr i8, i8* %base, i64 %off32.sext
/external/google-breakpad/src/third_party/libdisasm/
Dx86_insn.c33 return op_lst->op.data.absolute.offset.off32; in x86_get_address()
Dx86_format.c689 op->data.absolute.offset.off32, len ); in format_operand_att()
760 op->data.absolute.offset.off32, len ); in format_operand_native()
845 op->data.absolute.offset.off32, len ); in format_operand_xml()
947 op->data.absolute.offset.off32, len ); in format_operand_raw()
Dia32_operand.c120 &op->data.absolute.offset.off32, 4 ); in decode_operand_value()
Dlibdis.h150 uint32_t off32; /* loaded directly into EIP */ member
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-art-deps-rec.ll82 …%.lcssa550.off32 = phi i32 [ undef, %for.cond22.for.end_crit_edge.us.ur-lcssa ], [ %extract.t662, …
90 store i32 %.lcssa550.off32, i32* %19, align 4
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-postinc-distribute.ll189 %accReal.0.off32.lcssa = phi i32 [ %12, %while.cond.while.end_crit_edge ], [ 0, %entry ]
191 %accImag.0.off32.lcssa = phi i32 [ %15, %while.cond.while.end_crit_edge ], [ 0, %entry ]
196 …dava.v8i16(i32 0, i32 1, i32 0, i32 %accReal.0.off0.lcssa, i32 %accReal.0.off32.lcssa, <8 x i16> %…
203 …dava.v8i16(i32 0, i32 0, i32 1, i32 %accImag.0.off0.lcssa, i32 %accImag.0.off32.lcssa, <8 x i16> %…