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Searched refs:offset0 (Results 1 – 25 of 115) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
Dds-err.s10 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
18 ds_write2_b32 v2, v4, v6 offset0:1000000000
Dds.s17 ds_write_src2_b32 v2 offset0:4 offset1:8
21 ds_write_src2_b64 v2 offset0:4 offset1:8
25 ds_write2_b32 v2, v4, v6 offset0:4
29 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
37 ds_read2_b32 v[8:9], v2 offset0:4
41 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dload-local-i16.ll99 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
358 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
386 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
424 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
425 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
426 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
455 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
456 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
458 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
459 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:14 off…
[all …]
Dds-combine-with-dependence.ll9 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
10 ; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
42 ; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:27
43 ; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
74 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
75 ; GCN-NEXT: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:8 offset1:26
107 ; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
Dds_read2_offset_order.ll6 ; offset0 is larger than offset1
10 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3
12 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12
Ddagcombine-reassociate-bug.ll16 %offset0 = add i64 %offset, 1027
17 %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0
Dload-local-i32.ll69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
82 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7{{$}}
83 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5{{$}}
84 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
86 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offs…
87 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offs…
88 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offs…
/external/llvm-project/llvm/test/MC/AMDGPU/
Dds.s38 ds_write2_b32 v2, v4, v6 offset0:4
42 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
50 ds_read2_b32 v[8:9], v2 offset0:4
54 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8
250 ds_wrxchg2_rtn_b32 v[0:1], v0, v0, v0 offset0:127 offset1:255
258 ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255
459 ds_wrxchg2_rtn_b64 v[0:3], v0, v[1:2], v[0:1] offset0:127 offset1:255
467 ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255
Dds-err.s14 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
22 ds_write2_b32 v2, v4, v6 offset0:1000000000
26 ds_write2_b32 v2, v4, v6 offset0:0x100
/external/mesa3d/src/egl/wayland/wayland-drm/
Dwayland-drm.c63 int32_t offset0, int32_t stride0, in create_buffer() argument
80 buffer->offset[0] = offset0; in create_buffer()
139 int32_t offset0, int32_t stride0, in drm_create_planar_buffer() argument
160 offset0, stride0, offset1, stride1, offset2, stride2); in drm_create_planar_buffer()
168 int32_t offset0, int32_t stride0, in drm_create_prime_buffer() argument
173 offset0, stride0, offset1, stride1, offset2, stride2); in drm_create_prime_buffer()
/external/llvm/test/CodeGen/AMDGPU/
Dload-local-i16.ll54 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
68 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
242 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
259 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:1{{$}}
270 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
271 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
272 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
281 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
282 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4
[all …]
Dload-local-i32.ll39 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
49 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
50 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}}
59 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4{{$}}
60 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:5 offset1:6{{$}}
61 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7{{$}}
62 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}}
Dds_read2_offset_order.ll7 ; offset0 is larger than offset1
11 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3
12 ; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:14 offset1:12
Dlocal-64.ll125 ; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:15 offset…
135 ; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1
144 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:31 of…
145 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:29 of…
155 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:3 off…
156 ; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1
Ddagcombine-reassociate-bug.ll16 %offset0 = add i64 %offset, 1027
17 %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0
/external/brotli/c/enc/
Dbackward_references.c30 size_t offset0 = distance_plus_3 - (size_t)dist_cache[0]; in ComputeDistanceCode() local
36 } else if (offset0 < 7) { in ComputeDistanceCode()
37 return (0x9750468 >> (4 * offset0)) & 0xF; in ComputeDistanceCode()
/external/llvm/test/CodeGen/Mips/
Deh-return32.ll18 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
36 ; CHECK: lw $4, [[offset0]]($sp)
60 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
76 ; CHECK: lw $4, [[offset0]]($sp)
Deh-return64.ll19 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
37 ; CHECK: ld $4, [[offset0]]($sp)
63 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
79 ; CHECK: ld $4, [[offset0]]($sp)
/external/llvm-project/llvm/test/CodeGen/Mips/
Deh-return32.ll18 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
36 ; CHECK: lw $4, [[offset0]]($sp)
60 ; CHECK: sw $4, [[offset0:[0-9]+]]($sp)
76 ; CHECK: lw $4, [[offset0]]($sp)
Deh-return64.ll19 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
37 ; CHECK: ld $4, [[offset0]]($sp)
63 ; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
79 ; CHECK: ld $4, [[offset0]]($sp)
/external/llvm-project/polly/test/Isl/Ast/
Dsimple-run-time-condition.ll51 %offset0 = add nsw i64 %i, %p
52 %subscript0 = mul i64 %offset0, %m
75 %offset0.1 = add nsw i64 %i.1, %p
76 %subscript0.1 = mul i64 %offset0.1, %m
/external/tensorflow/tensorflow/tools/graph_transforms/
Dfold_old_batch_norms.cc242 std::vector<float> offset0(offset_values); in FuseBatchNormWithConvConcat() local
252 offset0.erase(offset0.begin() + split_cols, offset0.end()); in FuseBatchNormWithConvConcat()
261 FuseScaleOffsetToConvWeights(scale0, offset0, concat_node_match.inputs[0], in FuseBatchNormWithConvConcat()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DDSInstructions.td43 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
75 bits<8> offset0;
79 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
140 offset0:$offset0, offset1:$offset1, gds:$gds),
141 " $addr, $data0, $data1$offset0$offset1$gds"> {
207 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
208 " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
254 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
255 " $vdst, $addr$offset0$offset1$gds"> {
775 (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
[all …]
/external/abseil-cpp/absl/time/internal/cctz/src/
Dtime_zone_libc.cc252 int offset0, offset1; in MakeTime() local
253 if (make_time(cs, 0, &t0, &offset0) && make_time(cs, 1, &t1, &offset1)) { in MakeTime()
262 std::swap(offset0, offset1); in MakeTime()
267 if (offset0 < offset1) { in MakeTime()
/external/webrtc/third_party/abseil-cpp/absl/time/internal/cctz/src/
Dtime_zone_libc.cc252 int offset0, offset1; in MakeTime() local
253 if (make_time(cs, 0, &t0, &offset0) && make_time(cs, 1, &t1, &offset1)) { in MakeTime()
262 std::swap(offset0, offset1); in MakeTime()
267 if (offset0 < offset1) { in MakeTime()

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