Home
last modified time | relevance | path

Searched refs:opc (Results 1 – 25 of 277) sorted by relevance

12345678910>>...12

/external/llvm/lib/Target/XCore/
DXCoreInstrFormats.td36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
38 let Inst{15-11} = opc;
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
52 let Inst{31-27} = opc{8-4};
54 let Inst{19-16} = opc{3-0};
61 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
62 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
66 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
[all …]
/external/llvm-project/llvm/lib/Target/XCore/
DXCoreInstrFormats.td35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 let Inst{15-11} = opc;
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 let Inst{31-27} = opc{8-4};
53 let Inst{19-16} = opc{3-0};
60 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
61 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
65 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrFormats.td35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 let Inst{15-11} = opc;
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 let Inst{31-27} = opc{8-4};
53 let Inst{19-16} = opc{3-0};
60 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
61 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
65 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td1 class Enc_COPROC_VX_3op_v<bits<15> opc> : OpcodeHexagon {
6 let Inst{31-16} = { opc{14-4}, src2};
7 let Inst{13-0} = { opc{3}, src1, opc{2-0}, dst};
196 class Enc_COPROC_VX_cmp<bits<13> opc> : OpcodeHexagon {
201 let Inst{31-16} = { 0b00011, opc{12-7}, src2{4-0} };
202 let Inst{13-0} = { opc{6}, src1{4-0}, opc{5-0}, dst{1-0} };
244 class Enc_COPROC_VX_p2op<bits<5> opc> : OpcodeHexagon {
249 let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} };
250 let Inst{13-0} = { 1, src2{4-0}, opc{2-0}, dst{4-0} };
266 class Enc_COPROC_VX_2op<bits<6> opc> : OpcodeHexagon {
[all …]
/external/wpa_supplicant_8/src/crypto/
Dmilenage.c36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument
44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
67 tmp1[i] ^= opc[i]; in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument
96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345()
108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345()
114 tmp3[i] ^= opc[i]; in milenage_f2345()
124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345()
129 ck[i] ^= opc[i]; in milenage_f2345()
[all …]
/external/llvm-project/llvm/test/TableGen/
DDefmInsideMultiClass.td7 class Instruction<bits<4> opc, string Name> {
8 bits<4> opcode = opc;
12 multiclass basic_r<bits<4> opc> {
13 def rr : Instruction<opc, "rr">;
14 def rm : Instruction<opc, "rm">;
17 multiclass basic_s<bits<4> opc> {
18 defm SS : basic_r<opc>;
19 defm SD : basic_r<opc>;
22 multiclass basic_p<bits<4> opc> {
23 defm PS : basic_r<opc>;
[all …]
DLetInsideMultiClasses.td9 class Instruction<bits<4> opc, string Name> {
10 bits<4> opcode = opc;
15 multiclass basic_r<bits<4> opc> {
17 def rr : Instruction<opc, "rr">;
18 def rm : Instruction<opc, "rm">;
22 def rx : Instruction<opc, "rx">;
25 multiclass basic_ss<bits<4> opc> {
27 defm SS : basic_r<opc>;
30 defm SD : basic_r<opc>;
/external/llvm/test/TableGen/
DDefmInsideMultiClass.td7 class Instruction<bits<4> opc, string Name> {
8 bits<4> opcode = opc;
12 multiclass basic_r<bits<4> opc> {
13 def rr : Instruction<opc, "rr">;
14 def rm : Instruction<opc, "rm">;
17 multiclass basic_s<bits<4> opc> {
18 defm SS : basic_r<opc>;
19 defm SD : basic_r<opc>;
22 multiclass basic_p<bits<4> opc> {
23 defm PS : basic_r<opc>;
[all …]
DLetInsideMultiClasses.td9 class Instruction<bits<4> opc, string Name> {
10 bits<4> opcode = opc;
15 multiclass basic_r<bits<4> opc> {
17 def rr : Instruction<opc, "rr">;
18 def rm : Instruction<opc, "rm">;
22 def rx : Instruction<opc, "rx">;
25 multiclass basic_ss<bits<4> opc> {
27 defm SS : basic_r<opc>;
30 defm SD : basic_r<opc>;
/external/mesa3d/src/freedreno/afuc/
Ddisasm.c119 static void print_alu_name(afuc_opc opc, uint32_t instr) in print_alu_name() argument
121 if (opc == OPC_ADD) { in print_alu_name()
123 } else if (opc == OPC_ADDHI) { in print_alu_name()
125 } else if (opc == OPC_SUB) { in print_alu_name()
127 } else if (opc == OPC_SUBHI) { in print_alu_name()
129 } else if (opc == OPC_AND) { in print_alu_name()
131 } else if (opc == OPC_OR) { in print_alu_name()
133 } else if (opc == OPC_XOR) { in print_alu_name()
135 } else if (opc == OPC_NOT) { in print_alu_name()
137 } else if (opc == OPC_SHL) { in print_alu_name()
[all …]
Dasm.c131 afuc_opc opc; in emit_instructions() local
149 opc = OPC_NOP; in emit_instructions()
177 opc = tok2alu(ai->tok); in emit_instructions()
182 opc = OPC_ALU; in emit_instructions()
199 opc = OPC_MOVI; in emit_instructions()
208 opc = OPC_MOVI; in emit_instructions()
214 opc = OPC_ALU; in emit_instructions()
228 opc = OPC_CWRITE6; in emit_instructions()
230 opc = OPC_CREAD6; in emit_instructions()
232 opc = OPC_STORE6; in emit_instructions()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td258 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
269 let Inst{18-17} = opc{2-1};
270 let Inst{16} = opc{0};
276 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
279 multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
280 def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
281 def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
282 def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
283 def _D : sve_int_ptrue<0b11, opc, asm, PPR64, nxv2i1, op>;
385 class sve_int_pfalse<bits<6> opc, string asm>
[all …]
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrVec.td86 multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
89 def "" : RVM<opc, (outs RC:$vx), dag_in,
93 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
96 multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
97 defm "" : VLDbm<opcStr, opc, RC, dag_in>;
99 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
100 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
104 multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
105 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
107 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
[all …]
/external/mesa3d/src/freedreno/ir3/
Dinstr-a3xx.h53 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc) argument
265 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS)) argument
266 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1))) argument
268 const char *disasm_a3xx_instr_name(opc_t opc);
399 uint32_t opc : 4; member
506 uint32_t opc : 6; member
567 uint32_t opc : 4; member
575 switch (_OPC(3, cat3->opc)) { in instr_cat3_full()
625 uint32_t opc : 6; member
727 uint32_t opc : 5; member
[all …]
Dir3.c149 cat0->opc = instr->opc; in emit_cat0()
150 cat0->opc_hi = instr->opc >= 16; in emit_cat0()
210 unsigned absneg = ir3_cat2_absneg(instr->opc); in emit_cat2()
288 cat2->opc = instr->opc; in emit_cat2()
303 unsigned absneg = ir3_cat3_absneg(instr->opc); in emit_cat3()
307 switch (instr->opc) { in emit_cat3()
390 cat3->opc = instr->opc; in emit_cat3()
439 cat4->opc = instr->opc; in emit_cat4()
529 cat5->opc = instr->opc; in emit_cat5()
546 cat6->d = instr->cat6.d - (instr->opc == OPC_LDC ? 0 : 1); in emit_cat6_a6xx()
[all …]
Dir3.h173 opc_t opc; member
572 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
574 opc_t opc, int nreg);
649 return (opc_cat(instr->opc) == 0); in is_flow()
654 return instr->opc == OPC_KILL; in is_kill()
659 return instr->opc == OPC_NOP; in is_nop()
682 switch (instr->opc) { in is_same_type_mov()
725 if (instr->opc != OPC_MOV) in is_const_mov()
741 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3); in is_alu()
746 return (opc_cat(instr->opc) == 4); in is_sfu()
[all …]
Dir3_cp.c89 if (src_instr->opc == OPC_META_SPLIT) { in is_eligible_mov()
92 if (dst_instr->opc == OPC_META_COLLECT) in is_eligible_mov()
169 bool f_opcode = (is_cat2_float(instr->opc) || in lower_immed()
170 is_cat3_float(instr->opc)) ? true : false; in lower_immed()
268 if (!is_mad(instr->opc)) in try_swap_mad_two_srcs()
382 if ((opc_cat(instr->opc) == 3) && (n == 2) && in reg_cp()
392 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type)) in reg_cp()
394 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc)) in reg_cp()
429 debug_assert((opc_cat(instr->opc) == 1) || in reg_cp()
430 (opc_cat(instr->opc) == 6) || in reg_cp()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td798 multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
802 def r_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
808 def rk_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
817 def rkz_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
828 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
831 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
842 defm m_Int : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
851 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
853 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
[all …]
DX86InstrXOP.td14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DSVEInstrFormats.td264 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
275 let Inst{18-17} = opc{2-1};
276 let Inst{16} = opc{0};
282 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
286 multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
287 def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
288 def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
289 def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
290 def _D : sve_int_ptrue<0b11, opc, asm, PPR64, nxv2i1, op>;
499 class sve_int_pfalse<bits<6> opc, string asm>
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrFormats.td430 string opc, string asm, string cstr,
437 let AsmString = !strconcat(opc, "${p}", asm);
445 string opc, string asm, string cstr,
450 let AsmString = !strconcat(opc, asm);
461 string opc, string asm, string cstr,
471 let AsmString = !strconcat(opc, "${s}${p}", asm);
489 string opc, string asm, list<dag> pattern>
491 opc, asm, "", pattern>;
493 string opc, string asm, list<dag> pattern>
495 opc, asm, "", pattern>;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrFormats.td554 string opc, string asm, string cstr,
561 let AsmString = !strconcat(opc, "${p}", asm);
569 string opc, string asm, string cstr,
574 let AsmString = !strconcat(opc, asm);
585 string opc, string asm, string cstr,
595 let AsmString = !strconcat(opc, "${s}${p}", asm);
613 string opc, string asm, list<dag> pattern>
615 opc, asm, "", pattern>;
617 string opc, string asm, list<dag> pattern>
619 opc, asm, "", pattern>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrFormats.td548 string opc, string asm, string cstr,
555 let AsmString = !strconcat(opc, "${p}", asm);
563 string opc, string asm, string cstr,
568 let AsmString = !strconcat(opc, asm);
579 string opc, string asm, string cstr,
589 let AsmString = !strconcat(opc, "${s}${p}", asm);
607 string opc, string asm, list<dag> pattern>
609 opc, asm, "", pattern>;
611 string opc, string asm, list<dag> pattern>
613 opc, asm, "", pattern>;
[all …]
/external/mesa3d/src/freedreno/ir2/
Ddisasm-a2xx.c129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc } argument
442 #define INSTR(opc, name, fxn) [opc] = { name, fxn } argument
467 printf("%s", fetch_instructions[fetch->opc].name); in disasm_fetch()
468 fetch_instructions[fetch->opc].fxn(fetch); in disasm_fetch()
480 return (cf->opc == EXEC) || in cf_exec()
481 (cf->opc == EXEC_END) || in cf_exec()
482 (cf->opc == COND_EXEC) || in cf_exec()
483 (cf->opc == COND_EXEC_END) || in cf_exec()
484 (cf->opc == COND_PRED_EXEC) || in cf_exec()
485 (cf->opc == COND_PRED_EXEC_END) || in cf_exec()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td879 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
886 let Inst{7-5} = opc;
1045 // case opc of
1052 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1056 let Inst{24-21} = opc;
1062 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1069 class SpecialReturn<bits<4> opc, string asm>
1070 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1270 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
[all …]

12345678910>>...12