Home
last modified time | relevance | path

Searched refs:orns (Results 1 – 25 of 27) sorted by relevance

12

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dorns-diagnostics.s6 orns p0.h, p0/z, p0.h, p1.h label
11 orns p0.s, p0/z, p0.s, p1.s label
16 orns p0.d, p0/z, p0.d, p1.d label
24 orns p0.b, p0/m, p1.b, p2.b label
Dorns.s10 orns p0.b, p0/z, p0.b, p0.b label
16 orns p15.b, p15/z, p15.b, p15.b label
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s186 orns r0, r1, #1 label
188 orns r0, r1, r2 label
190 orns r0, r1, r2, LSL #1 label
618 # CHECK-NEXT: 1 1 0.50 orns r0, r1, #1
620 # CHECK-NEXT: 1 1 0.50 orns r0, r1, r2
622 # CHECK-NEXT: 1 2 1.00 orns r0, r1, r2, lsl #1
1058 …0.50 - - - - - - - - - - - orns r0, r1, #1
1060 …0.50 - - - - - - - - - - - orns r0, r1, r2
1062 …- - - - - 1.00 - - - - - orns r0, r1, r2, lsl #1
Dm4-int.s192 orns r0, r1, #1 label
194 orns r0, r1, r2 label
196 orns r0, r1, r2, LSL #1 label
639 # CHECK-NEXT: 1 1 1.00 orns r0, r1, #1
641 # CHECK-NEXT: 1 1 1.00 orns r0, r1, r2
643 # CHECK-NEXT: 1 1 1.00 orns r0, r1, r2, lsl #1
1077 # CHECK-NEXT: 1.00 orns r0, r1, #1
1079 # CHECK-NEXT: 1.00 orns r0, r1, r2
1081 # CHECK-NEXT: 1.00 orns r0, r1, r2, lsl #1
Dcortex-a57-thumb.s430 orns r4, r5, r6
432 orns r4, r5, r6, lsr #5
434 orns r4, r5, r6, asr #5
1338 # CHECK-NEXT: 1 1 0.50 orns r4, r5, r6
1340 # CHECK-NEXT: 1 2 1.00 orns r4, r5, r6, lsr #5
1342 # CHECK-NEXT: 1 2 1.00 orns r4, r5, r6, asr #5
2252 # CHECK-NEXT: - 0.50 0.50 - - - - - orns r4, r5, r6
2254 # CHECK-NEXT: - - - - 1.00 - - - orns r4, r5, r6, lsr #5
2256 # CHECK-NEXT: - - - - 1.00 - - - orns r4, r5, r6, asr #5
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs535 0x75,0xea,0x06,0x04 = orns r4, r5, r6
537 0x75,0xea,0x56,0x14 = orns r4, r5, r6, lsr #5
539 0x75,0xea,0x66,0x14 = orns r4, r5, r6, asr #5
/external/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s1680 orns r4, r5, r6
1682 orns r4, r5, r6, lsr #5
1684 orns r4, r5, r6, asr #5
1689 @ CHECK: orns r4, r5, r6 @ encoding: [0x75,0xea,0x06,0x04]
1691 @ CHECK: orns r4, r5, r6, lsr #5 @ encoding: [0x75,0xea,0x56,0x14]
1693 @ CHECK: orns r4, r5, r6, asr #5 @ encoding: [0x75,0xea,0x66,0x14]
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-thumb2-instructions.s1875 orns r4, r5, r6
1877 orns r4, r5, r6, lsr #5
1879 orns r4, r5, r6, asr #5
1884 @ CHECK: orns r4, r5, r6 @ encoding: [0x75,0xea,0x06,0x04]
1886 @ CHECK: orns r4, r5, r6, lsr #5 @ encoding: [0x75,0xea,0x56,0x14]
1888 @ CHECK: orns r4, r5, r6, asr #5 @ encoding: [0x75,0xea,0x66,0x14]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-operand-const-t32.cc63 M(orns) \
Dtest-assembler-cond-rd-rn-operand-rm-t32.cc63 M(orns) \
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc63 M(orns) \
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc63 M(orns) \
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1221 # CHECK: orns r4, r5, r6
1223 # CHECK: orns r4, r5, r6, lsr #5
1225 # CHECK: orns r4, r5, r6, asr #5
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1221 # CHECK: orns r4, r5, r6
1223 # CHECK: orns r4, r5, r6, lsr #5
1225 # CHECK: orns r4, r5, r6, asr #5
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.cc1060 orns(cond, rd, rn, ~imm); in Delegate()
Dassembler-aarch32.h2724 void orns(Condition cond, Register rd, Register rn, const Operand& operand);
2725 void orns(Register rd, Register rn, const Operand& operand) { in orns() function
2726 orns(al, rd, rn, operand); in orns()
Ddisasm-aarch32.h952 void orns(Condition cond, Register rd, Register rn, const Operand& operand);
Ddisasm-aarch32.cc2012 void Disassembler::orns(Condition cond, in orns() function in vixl::aarch32::Disassembler
8636 orns(CurrentCond(), Register(rd), Register(rn), imm); in DecodeT32()
19200 orns(CurrentCond(), in DecodeT32()
19223 orns(CurrentCond(), in DecodeT32()
Dassembler-aarch32.cc7737 void Assembler::orns(Condition cond, in orns() function in vixl::aarch32::Assembler
7776 Delegate(kOrns, &Assembler::orns, cond, rd, rn, operand); in orns()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td325 defm ORNS_PPzPP : sve_int_pred_log<0b1101, "orns", null_frag>;
/external/vixl/src/aarch64/
Dassembler-aarch64.h5070 void orns(const PRegisterWithLaneSize& pd,
Dassembler-sve-aarch64.cc6080 void Assembler::orns(const PRegisterWithLaneSize& pd, in orns() function in vixl::aarch64::Assembler
Dmacro-assembler-aarch64.h5431 orns(pd, pg, pn, pm); in Orns()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td653 defm ORNS_PPzPP : sve_int_pred_log<0b1101, "orns", null_frag>;
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc5989 COMPARE_PREFIX(orns(p10.VnB(), p11.Zeroing(), p0.VnB(), p15.VnB()), in TEST()

12