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Searched refs:p_bits_per_lane (Results 1 – 3 of 3) sorted by relevance

/external/vixl/test/aarch64/
Dtest-utils-aarch64.h189 unsigned p_bits_per_lane, in preg_lane() argument
192 VIXL_ASSERT(lane < GetSVELaneCount(p_bits_per_lane * kZRegBitsPerPRegBit)); in preg_lane()
196 VIXL_ASSERT(IsPowerOf2(p_bits_per_lane)); in preg_lane()
197 VIXL_ASSERT(p_bits_per_lane <= kChunkSizeInBits); in preg_lane()
199 int chunk_index = (lane * p_bits_per_lane) / kChunkSizeInBits; in preg_lane()
200 int bit_index = (lane * p_bits_per_lane) % kChunkSizeInBits; in preg_lane()
202 return (chunk >> bit_index) & GetUintMask(p_bits_per_lane); in preg_lane()
Dtest-utils-aarch64.cc391 unsigned p_bits_per_lane = reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit; in EqualSVELane() local
392 VIXL_ASSERT(IsUintN(p_bits_per_lane, expected)); in EqualSVELane()
393 expected &= GetUintMask(p_bits_per_lane); in EqualSVELane()
395 uint64_t result = core->preg_lane(reg.GetCode(), p_bits_per_lane, lane); in EqualSVELane()
397 unsigned lane_size_in_hex_chars = (p_bits_per_lane + 3) / 4; in EqualSVELane()
Dtest-assembler-sve-aarch64.cc188 int p_bits_per_lane = pd.GetLaneSizeInBits() / kZRegBitsPerPRegBit; in Initialise() local
189 VIXL_ASSERT((64 % p_bits_per_lane) == 0); in Initialise()
190 VIXL_ASSERT((N * p_bits_per_lane) <= kPRegMaxSize); in Initialise()
192 uint64_t p_lane_mask = GetUintMask(p_bits_per_lane); in Initialise()
200 bit += p_bits_per_lane; in Initialise()