Searched refs:pipelined (Results 1 – 25 of 87) sorted by relevance
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| /external/XNNPACK/scripts/ |
| D | generate-f32-spmm.sh | 16 tools/xngen src/f32-spmm/scalar-pipelined.c.in -D MR=1 -D NR=1 -o src/f32-spmm/gen/1x1-minmax-scala…
17 tools/xngen src/f32-spmm/scalar-pipelined.c.in -D MR=2 -D NR=1 -o src/f32-spmm/gen/2x1-minmax-scala…
18 tools/xngen src/f32-spmm/scalar-pipelined.c.in -D MR=4 -D NR=1 -o src/f32-spmm/gen/4x1-minmax-scala…
19 tools/xngen src/f32-spmm/scalar-pipelined.c.in -D MR=8 -D NR=1 -o src/f32-spmm/gen/8x1-minmax-scala…
59 tools/xngen src/f32-spmm/neon-pipelined.c.in -D MR=4 -D NR=1 -D FMA=0 -o src/f32-spmm/gen/4x1-minm…
60 tools/xngen src/f32-spmm/neon-pipelined.c.in -D MR=8 -D NR=1 -D FMA=0 -o src/f32-spmm/gen/8x1-minm…
61 tools/xngen src/f32-spmm/neon-pipelined.c.in -D MR=16 -D NR=1 -D FMA=0 -o src/f32-spmm/gen/16x1-min…
62 tools/xngen src/f32-spmm/neon-pipelined.c.in -D MR=32 -D NR=1 -D FMA=0 -o src/f32-spmm/gen/32x1-min…
64 tools/xngen src/f32-spmm/neon-pipelined.c.in -D MR=4 -D NR=1 -D FMA=1 -o src/f32-spmm/gen/4x1-minm…
65 tools/xngen src/f32-spmm/neon-pipelined.c.in -D MR=8 -D NR=1 -D FMA=1 -o src/f32-spmm/gen/8x1-minm…
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | swp-chain-refs.ll | 6 ; which enables the loop to be pipelined. In this test, the loop should
7 ; not be pipelined when the chained references are constrained correctly.
9 ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
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| D | swp-multi-loops.ll | 5 ; Check if the first loop is pipelined.
12 ; Check if the second loop is pipelined.
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| D | swp-subreg.ll | 6 ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
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| D | swp-const-tc2.ll | 3 ; Test that we fixup a pipelined loop correctly when the number of
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| D | swp-swap.ll | 6 ; STATS-NOT: 1 pipeliner - Number of loops software pipelined
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| D | swp-tfri.ll | 6 ; STATS: 1 pipeliner - Number of loops software pipelined
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| D | swp-phi-dep.ll | 3 ; Check that the pipelined code uses the proper address in the
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| D | swp-lots-deps.ll | 4 ; STATS: 1 pipeliner - Number of loops software pipelined
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| D | swp-matmul-bitext.ll | 4 ; function. The pipelined code should have two packets.
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| D | swp-const-tc1.ll | 8 ; Test that we change the CFG correctly for pipelined loops where the trip
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| D | swp-epilog-reuse-1.ll | 6 ; Phi. When the loop is pipelined, the Phi that generates the operand value
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| D | swp-stages5.ll | 3 ; Very similar to swp-stages4.ll, but the pipelined schedule is a little
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | hsw_queryobj.c | 410 const bool pipelined) in store_query_result_reg() argument
420 (pipelined ? MI_STORE_REGISTER_MEM_PREDICATE : 0) | in store_query_result_reg()
440 const bool pipelined = brw_is_query_pipelined(query); in hsw_store_query_result() local
446 } else if (pname == GL_QUERY_RESULT_AVAILABLE && !pipelined) { in hsw_store_query_result()
456 if (pipelined) in hsw_store_query_result()
459 pipelined); in hsw_store_query_result()
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| /external/XNNPACK/tools/ |
| D | generate-spmm-test.py | 449 pipelined = bool(ukernel_spec.get("pipelined", False))
455 test_case = generate_test_cases(name, mr, nr, k_block, pipelined, isa)
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| D | generate-dwconv-test.py | 361 pipelined = bool(ukernel_spec.get("pipelined", False))
368 test_case = generate_test_cases(name, cr, kr, cr, pipelined, isa)
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| D | generate-gemm-test.py | 844 pipelined = bool(ukernel_spec.get("pipelined", False))
852 name, mr, nr, kr, sr, k_block, pipelined, isa)
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| D | generate-dwconv2d-chw-test.py | 320 pipelined = bool(ukernel_spec.get("pipelined", False))
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | swp-multi-loops.ll | 5 ; Check if the first loop is pipelined.
12 ; Check if the second loop is pipelined.
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| D | swp-matmul-bitext.ll | 5 ; function. The pipelined code should have two packets.
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| /external/tensorflow/tensorflow/core/protobuf/tpu/ |
| D | tpu_embedding_configuration.proto | 64 // pipelined with that of the TensorCore. This parameter only affects results
68 // false: The execution of the sparse core is not pipelined with that of the
76 // true: The execution of the sparse core is pipelined with that of the
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVSchedRocket.td | 157 // FP division unit on Rocket is not pipelined, so set resource cycles to latency.
163 // FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVSchedRocket64.td | 144 // FP Divide unit on Rocket is not pipelined, so set resource cycles to latency
150 // FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency
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| D | RISCVSchedRocket32.td | 124 // FP Divide unit on Rocket is not pipelined, so set resource cycles to latency
130 // FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/vect/ |
| D | vect-shuffle.ll | 8 ; CHECK: Number of loops software pipelined
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