/external/strace/tests/ |
D | ioctl_rtc.c | 83 TAIL_ALLOC_OBJECT_CONST_PTR(struct rtc_pll_info, pll); in main() 84 fill_memory(pll, sizeof(*pll)); in main() 171 ioctl(-1, RTC_PLL_SET, pll); in main() 175 pll->pll_ctrl, pll->pll_value, pll->pll_max, pll->pll_min, in main() 176 pll->pll_posmult, pll->pll_negmult, pll->pll_clock); in main()
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/external/strace/tests-m32/ |
D | ioctl_rtc.c | 83 TAIL_ALLOC_OBJECT_CONST_PTR(struct rtc_pll_info, pll); in main() 84 fill_memory(pll, sizeof(*pll)); in main() 171 ioctl(-1, RTC_PLL_SET, pll); in main() 175 pll->pll_ctrl, pll->pll_value, pll->pll_max, pll->pll_min, in main() 176 pll->pll_posmult, pll->pll_negmult, pll->pll_clock); in main()
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/external/strace/tests-mx32/ |
D | ioctl_rtc.c | 83 TAIL_ALLOC_OBJECT_CONST_PTR(struct rtc_pll_info, pll); in main() 84 fill_memory(pll, sizeof(*pll)); in main() 171 ioctl(-1, RTC_PLL_SET, pll); in main() 175 pll->pll_ctrl, pll->pll_value, pll->pll_max, pll->pll_min, in main() 176 pll->pll_posmult, pll->pll_negmult, pll->pll_clock); in main()
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/external/strace/ |
D | rtc.c | 79 struct_rtc_pll_info pll; in decode_rtc_pll_info() local 81 if (!umove_or_printaddr(tcp, addr, &pll)) in decode_rtc_pll_info() 84 pll.pll_ctrl, pll.pll_value, pll.pll_max, pll.pll_min, in decode_rtc_pll_info() 85 pll.pll_posmult, pll.pll_negmult, (long) pll.pll_clock); in decode_rtc_pll_info()
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/external/arm-trusted-firmware/drivers/st/clk/ |
D | stm32mp1_clk.c | 756 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) in stm32mp1_pll_get_fref() argument 758 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); in stm32mp1_pll_get_fref() 761 return stm32mp1_clk_get_fixed(pll->refclk[src]); in stm32mp1_pll_get_fref() 770 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) in stm32mp1_pll_get_fvco() argument 776 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); in stm32mp1_pll_get_fvco() 777 fracr = mmio_read_32(rcc_base + pll->pllxfracr); in stm32mp1_pll_get_fvco() 782 refclk = stm32mp1_pll_get_fref(pll); in stm32mp1_pll_get_fvco() 809 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq() local 817 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq() 820 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); in stm32mp1_read_pll_freq() [all …]
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/external/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/ |
D | pm_api_sys.c | 950 struct pm_pll *pll; in pm_clock_enable() local 953 pll = pm_clock_get_pll(clock_id); in pm_clock_enable() 954 if (pll) in pm_clock_enable() 955 return pm_clock_pll_enable(pll); in pm_clock_enable() 973 struct pm_pll *pll; in pm_clock_disable() local 976 pll = pm_clock_get_pll(clock_id); in pm_clock_disable() 977 if (pll) in pm_clock_disable() 978 return pm_clock_pll_disable(pll); in pm_clock_disable() 997 struct pm_pll *pll; in pm_clock_getstate() local 1002 pll = pm_clock_get_pll(clock_id); in pm_clock_getstate() [all …]
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D | pm_api_ioctl.c | 364 (unsigned int pll, unsigned int mode) in pm_ioctl_set_pll_frac_mode() argument 366 return pm_clock_set_pll_mode(pll, mode); in pm_ioctl_set_pll_frac_mode() 380 (unsigned int pll, unsigned int *mode) in pm_ioctl_get_pll_frac_mode() argument 382 return pm_clock_get_pll_mode(pll, mode); in pm_ioctl_get_pll_frac_mode() 397 (unsigned int pll, unsigned int data) in pm_ioctl_set_pll_frac_data() argument 403 status = pm_clock_get_pll_node_id(pll, &pll_nid); in pm_ioctl_set_pll_frac_data() 421 (unsigned int pll, unsigned int *data) in pm_ioctl_get_pll_frac_data() argument 427 status = pm_clock_get_pll_node_id(pll, &pll_nid); in pm_ioctl_get_pll_frac_data()
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D | pm_api_clock.c | 2760 struct pm_pll *pll = pm_clock_get_pll(clock_id); in pm_clock_get_pll_node_id() local 2762 if (pll) { in pm_clock_get_pll_node_id() 2763 *node_id = pll->nid; in pm_clock_get_pll_node_id() 2801 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll) in pm_clock_pll_enable() argument 2803 if (!pll) in pm_clock_pll_enable() 2807 if (pll->mode == PLL_FRAC_MODE) in pm_clock_pll_enable() 2808 return pm_pll_set_mode(pll->nid, PM_PLL_MODE_FRACTIONAL); in pm_clock_pll_enable() 2810 return pm_pll_set_mode(pll->nid, PM_PLL_MODE_INTEGER); in pm_clock_pll_enable() 2822 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll) in pm_clock_pll_disable() argument 2824 if (!pll) in pm_clock_pll_disable() [all …]
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D | pm_api_clock.h | 318 enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll); 319 enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll); 320 enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll, 322 enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll, 325 enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
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/external/arm-trusted-firmware/fdts/ |
D | stm32mp15xx-osd32.dtsi | 252 pll1: st,pll@0 { 253 compatible = "st,stm32mp1-pll"; 260 pll2: st,pll@1 { 261 compatible = "st,stm32mp1-pll"; 268 pll3: st,pll@2 { 269 compatible = "st,stm32mp1-pll"; 276 pll4: st,pll@3 { 277 compatible = "st,stm32mp1-pll";
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D | stm32mp15xx-dkx.dtsi | 261 pll1: st,pll@0 { 262 compatible = "st,stm32mp1-pll"; 269 pll2: st,pll@1 { 270 compatible = "st,stm32mp1-pll"; 277 pll3: st,pll@2 { 278 compatible = "st,stm32mp1-pll"; 285 pll4: st,pll@3 { 286 compatible = "st,stm32mp1-pll";
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D | stm32mp157a-avenger96.dts | 243 pll1: st,pll@0 { 244 compatible = "st,stm32mp1-pll"; 251 pll2: st,pll@1 { 252 compatible = "st,stm32mp1-pll"; 259 pll3: st,pll@2 { 260 compatible = "st,stm32mp1-pll"; 267 pll4: st,pll@3 { 268 compatible = "st,stm32mp1-pll";
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D | stm32mp157c-ed1.dts | 271 pll1: st,pll@0 { 277 pll2: st,pll@1 { 283 pll3: st,pll@2 { 289 pll4: st,pll@3 {
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/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/ |
D | soc.c | 107 uint32_t *pll = slp_data.pll_con[pll_id]; in pll_save() local 109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save() 110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save() 111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save() 112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
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/external/libwebsockets/lib/misc/ |
D | lws-struct-sqlite.c | 87 long long *pll; in lws_struct_sq3_deser_cb() local 88 pll = (long long *)(u + map->ofs); in lws_struct_sq3_deser_cb() 89 *pll = atoll(cv[n]); in lws_struct_sq3_deser_cb() 119 unsigned long long *pll; in lws_struct_sq3_deser_cb() local 120 pll = (unsigned long long *)(u + map->ofs); in lws_struct_sq3_deser_cb() 121 *pll = atoll(cv[n]); in lws_struct_sq3_deser_cb()
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D | lws-struct-lejp.c | 281 long long *pll; in lws_struct_default_lejp_cb() local 282 pll = (long long *)(u + map->ofs); in lws_struct_default_lejp_cb() 283 *pll = atoll(ctx->buf); in lws_struct_default_lejp_cb() 305 unsigned long long *pll; in lws_struct_default_lejp_cb() local 306 pll = (unsigned long long *)(u + map->ofs); in lws_struct_default_lejp_cb() 307 *pll = atoll(ctx->buf); in lws_struct_default_lejp_cb()
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/external/llvm-project/llvm/test/MC/Mips/mips4/ |
D | invalid-mips5.s | 15 …pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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/external/llvm-project/llvm/test/MC/Mips/mips64r6/ |
D | invalid-mips5.s | 16 …pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
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/external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r3/ |
D | valid-fp64.txt | 23 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
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D | valid-fp64-el.txt | 23 0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
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/external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r2/ |
D | valid-fp64-el.txt | 23 0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
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D | valid-fp64.txt | 23 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
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/external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r5/ |
D | valid-fp64.txt | 23 0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30
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D | valid-fp64-el.txt | 23 0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30
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/external/llvm/test/MC/Mips/mips3/ |
D | invalid-mips5-wrong-error.s | 42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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