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Searched refs:pp_txfilter (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_tex.c64 t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D); in radeonSetTexWrap()
68 t->pp_txfilter |= RADEON_CLAMP_S_WRAP; in radeonSetTexWrap()
71 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; in radeonSetTexWrap()
75 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST; in radeonSetTexWrap()
78 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; in radeonSetTexWrap()
82 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR; in radeonSetTexWrap()
85 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; in radeonSetTexWrap()
89 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST; in radeonSetTexWrap()
92 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; in radeonSetTexWrap()
102 t->pp_txfilter |= RADEON_CLAMP_T_WRAP; in radeonSetTexWrap()
[all …]
Dradeon_texstate.c614 t->pp_txfilter |= tx_table[texFormat].filter; in radeonSetTexBuffer2()
724 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; in import_tex_obj_state()
930 t->pp_txfilter &= ~RADEON_YUV_TO_RGB; in setup_hardware_state()
933 t->pp_txfilter |= table[ firstImage->TexFormat ].filter; in setup_hardware_state()
941 t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; in setup_hardware_state()
942 t->pp_txfilter |= (t->maxLod - t->minLod) << RADEON_MAX_MIP_LEVEL_SHIFT; in setup_hardware_state()
1002 if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) in radeon_validate_texture()
Dradeon_common_context.h204 GLuint pp_txfilter; /* hardware register values */ member
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_tex.c74 t->pp_txfilter &= ~(R200_CLAMP_S_MASK | R200_CLAMP_T_MASK | R200_BORDER_MODE_D3D); in r200SetTexWrap()
78 t->pp_txfilter |= R200_CLAMP_S_WRAP; in r200SetTexWrap()
81 t->pp_txfilter |= R200_CLAMP_S_CLAMP_GL; in r200SetTexWrap()
85 t->pp_txfilter |= R200_CLAMP_S_CLAMP_LAST; in r200SetTexWrap()
88 t->pp_txfilter |= R200_CLAMP_S_CLAMP_GL; in r200SetTexWrap()
92 t->pp_txfilter |= R200_CLAMP_S_MIRROR; in r200SetTexWrap()
95 t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_GL; in r200SetTexWrap()
99 t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_LAST; in r200SetTexWrap()
102 t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_GL; in r200SetTexWrap()
112 t->pp_txfilter |= R200_CLAMP_T_WRAP; in r200SetTexWrap()
[all …]
Dr200_texstate.c709 t->pp_txfilter |= tx_table_le[texFormat].filter; in r200SetTexBuffer2()
984 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; in import_tex_obj_state()
1319 t->pp_txfilter &= ~R200_YUV_TO_RGB; in setup_hardware_state()
1322 t->pp_txfilter |= table[ firstImage->TexFormat ].filter; in setup_hardware_state()
1332 t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK; in setup_hardware_state()
1333 t->pp_txfilter |= ((t->maxLod) << R200_MAX_MIP_LEVEL_SHIFT) in setup_hardware_state()
1336 if ( t->pp_txfilter & in setup_hardware_state()
Dradeon_common_context.h204 GLuint pp_txfilter; /* hardware register values */ member
/external/igt-gpu-tools/include/drm-uapi/
Dradeon_drm.h409 unsigned int pp_txfilter; member
/external/libdrm/include/drm/
Dradeon_drm.h409 unsigned int pp_txfilter; member
/external/kernel-headers/original/uapi/drm/
Dradeon_drm.h409 unsigned int pp_txfilter; member