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Searched refs:ptrue (Results 1 – 25 of 96) sorted by relevance

12 3 4

/external/llvm-project/llvm/test/MC/AArch64/SVE/
D	ptrue.s	`14 ptrue p0.b, pow2 label 20 ptrue p0.h, pow2 label 26 ptrue p0.s, pow2 label 32 ptrue p0.d, pow2 label 42 ptrue p15.b label 48 ptrue p15.h label 54 ptrue p15.s label 60 ptrue p15.d label 70 ptrue p7.s, #1 label 76 ptrue p7.s, vl1 label [all …]`
D	ptrue-diagnostics.s	`7 ptrue p0.s, vl512 label 12 ptrue p0.s, vl9 label 21 ptrue p0.s, #-1 label 26 ptrue p0.s, #32 label`
/external/llvm-project/llvm/test/CodeGen/AArch64/
D	sve-intrinsics-pred-creation.ll	13 ; CHECK: ptrue p0.b, pow2 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0) 21 ; CHECK: ptrue p0.h, vl1 23 %out = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 1) 29 ; CHECK: ptrue p0.s, mul3 31 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 30) 37 ; CHECK: ptrue p0.d 39 %out = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 43 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern) 44 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 %pattern) [all …]
D	sve-fcvt.ll	`15 ; CHECK-NEXT: ptrue p0.d 25 ; CHECK-NEXT: ptrue p0.s 35 ; CHECK-NEXT: ptrue p0.d 45 ; CHECK-NEXT: ptrue p0.d 59 ; CHECK-NEXT: ptrue p0.d 69 ; CHECK-NEXT: ptrue p0.s 79 ; CHECK-NEXT: ptrue p0.d 89 ; CHECK-NEXT: ptrue p0.d 103 ; CHECK-NEXT: ptrue p0.d 113 ; CHECK-NEXT: ptrue p0.d [all …]`
D	sve-fp-rounding.ll	`9 ; CHECK-NEXT: ptrue p0.h 19 ; CHECK-NEXT: ptrue p0.s 29 ; CHECK-NEXT: ptrue p0.d 39 ; CHECK-NEXT: ptrue p0.s 49 ; CHECK-NEXT: ptrue p0.d 59 ; CHECK-NEXT: ptrue p0.d 71 ; CHECK-NEXT: ptrue p0.h 81 ; CHECK-NEXT: ptrue p0.s 91 ; CHECK-NEXT: ptrue p0.d 101 ; CHECK-NEXT: ptrue p0.s [all …]`
D	sve-fcmp.ll	`11 ; CHECK-NEXT: ptrue p0.s 20 ; CHECK-NEXT: ptrue p0.s 29 ; CHECK-NEXT: ptrue p0.s 38 ; CHECK-NEXT: ptrue p0.s 47 ; CHECK-NEXT: ptrue p0.s 56 ; CHECK-NEXT: ptrue p0.s 65 ; CHECK-NEXT: ptrue p0.s 75 ; CHECK-NEXT: ptrue p0.s 85 ; CHECK-NEXT: ptrue p0.s 95 ; CHECK-NEXT: ptrue p0.s [all …]`
D	sve-int-reduce.ll	`13 ; CHECK-NEXT: ptrue p0.b 24 ; CHECK-NEXT: ptrue p0.h 35 ; CHECK-NEXT: ptrue p0.s 46 ; CHECK-NEXT: ptrue p0.d 59 ; CHECK-NEXT: ptrue p0.b 70 ; CHECK-NEXT: ptrue p0.h 81 ; CHECK-NEXT: ptrue p0.s 92 ; CHECK-NEXT: ptrue p0.d 105 ; CHECK-NEXT: ptrue p0.b 116 ; CHECK-NEXT: ptrue p0.h [all …]`
D	sve-ld1-addressing-mode-reg-imm.ll	`13 ; CHECK-NEXT: ptrue p0.b 24 ; CHECK-NEXT: ptrue p0.b 35 ; CHECK-NEXT: ptrue p0.b 48 ; CHECK-NEXT: ptrue p0.b 61 ; CHECK-NEXT: ptrue p0.b 74 ; CHECK-NEXT: ptrue p0.h 87 ; CHECK-NEXT: ptrue p0.s 100 ; CHECK-NEXT: ptrue p0.d 111 ; CHECK-NEXT: ptrue p0.d 112 ; CHECK-NEXT: ptrue p1.s [all …]`
D	sve-fixed-length-log-reduce.ll	`21 ; NO_SVE-NOT: ptrue 30 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl8 41 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl16 51 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl32 63 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64 70 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 86 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128 98 ; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256 111 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl4 122 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl8 [all …]`
D	sve-int-pred-reduce.ll	`13 ; CHECK-NEXT: ptrue p1.b 25 ; CHECK-NEXT: ptrue p1.h 37 ; CHECK-NEXT: ptrue p1.s 49 ; CHECK-NEXT: ptrue p1.d 63 ; CHECK-NEXT: ptrue p1.b 74 ; CHECK-NEXT: ptrue p1.h 85 ; CHECK-NEXT: ptrue p1.s 96 ; CHECK-NEXT: ptrue p1.d 109 ; CHECK-NEXT: ptrue p1.b 120 ; CHECK-NEXT: ptrue p1.h [all …]`
D	llvm-ir-to-intrinsic.ll	`13 ; CHECK-NEXT: ptrue p0.s 41 ; CHECK-NEXT: ptrue p0.s 55 ; CHECK-NEXT: ptrue p0.s 65 ; CHECK-NEXT: ptrue p0.d 75 ; CHECK-NEXT: ptrue p0.s 86 ; CHECK-NEXT: ptrue p0.d 98 ; CHECK-NEXT: ptrue p0.d 115 ; CHECK-NEXT: ptrue p0.s 133 ; CHECK-NEXT: ptrue p0.b 145 ; CHECK-NEXT: ptrue p0.s [all …]`
D	sve-fixed-length-fp-reduce.ll	`21 ; NO_SVE-NOT: ptrue 30 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl4 40 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl8 49 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 60 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 67 ; VBITS_EQ_256-NEXT: ptrue [[PG:p[0-9]+]].h, vl16 80 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 91 ; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 103 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl2 113 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl4 [all …]`
D	sve-st1-addressing-mode-reg-imm.ll	`13 ; CHECK-NEXT: ptrue p0.b 24 ; CHECK-NEXT: ptrue p0.b 35 ; CHECK-NEXT: ptrue p0.b 48 ; CHECK-NEXT: ptrue p0.b 61 ; CHECK-NEXT: ptrue p0.b 74 ; CHECK-NEXT: ptrue p0.h 87 ; CHECK-NEXT: ptrue p0.s 100 ; CHECK-NEXT: ptrue p0.d 115 ; CHECK-NEXT: ptrue p0.d 128 ; CHECK-NEXT: ptrue p0.s [all …]`
D	sve-fixed-length-int-reduce.ll	`21 ; NO_SVE-NOT: ptrue 47 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl32 59 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64 66 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 81 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128 93 ; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256 123 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 135 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 142 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 157 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 [all …]`
D	sve-fixed-length-splat-vector.ll	`21 ; NO_SVE-NOT: ptrue 50 ; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl32 62 ; VBITS_GE_512-DAG: ptrue [[PG:p[0-9]+]].b, vl64 68 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32 82 ; VBITS_GE_1024-DAG: ptrue [[PG:p[0-9]+]].b, vl128 94 ; VBITS_GE_2048-DAG: ptrue [[PG:p[0-9]+]].b, vl256 126 ; CHECK-DAG: ptrue [[PG:p[0-9]+]].h, vl16 138 ; VBITS_GE_512-DAG: ptrue [[PG:p[0-9]+]].h, vl32 144 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 158 ; VBITS_GE_1024-DAG: ptrue [[PG:p[0-9]+]].h, vl64 [all …]`
D	sve-fixed-length-int-extends.ll	`32 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 53 ; CHECK: ptrue [[PG:p[0-9]+]].d, vl4 71 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 85 ; VBITS_GE_512-NEXT: ptrue [[PG:p[0-9]+]].h, vl32 99 ; VBITS_GE_1024-NEXT: ptrue [[PG:p[0-9]+]].h, vl64 113 ; VBITS_GE_2048-NEXT: ptrue [[PG:p[0-9]+]].h, vl128 129 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 141 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 153 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 168 ; VBITS_GE_1024-NEXT: ptrue [[PG:p[0-9]+]].s, vl32 [all …]`
D	sve-intrinsic-opts-ptest.ll	9 ; OPT: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0) 13 %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0) 23 ; OPT: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 27 %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) 36 ; OPT: %mask = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 0) 40 %mask = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 0) 59 ; OPT: %mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0) 63 %mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 0) 70 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32) 71 declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32) [all …]
D	sve-fixed-length-int-select.ll	`21 ; NO_SVE-NOT: ptrue 43 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]] 44 ; CHECK: ptrue [[PG1:p[0-9]+]].b 63 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]] 64 ; CHECK: ptrue [[PG1:p[0-9]+]].b 83 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]] 84 ; CHECK: ptrue [[PG1:p[0-9]+]].b 103 ; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]] 104 ; CHECK: ptrue [[PG1:p[0-9]+]].b 141 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]] [all …]`
D	sve-fp.ll	`20 ; CHECK-NEXT: ptrue p0.s 30 ; CHECK-NEXT: ptrue p0.d 49 ; CHECK-NEXT: ptrue p0.d 68 ; CHECK-NEXT: ptrue p0.h 78 ; CHECK-NEXT: ptrue p0.s 88 ; CHECK-NEXT: ptrue p0.d 98 ; CHECK-NEXT: ptrue p0.s 108 ; CHECK-NEXT: ptrue p0.d 118 ; CHECK-NEXT: ptrue p0.d 137 ; CHECK-NEXT: ptrue p0.s [all …]`
D	sve-split-fcvt.ll	`14 ; CHECK-NEXT: ptrue p0.s 27 ; CHECK-NEXT: ptrue p0.d 41 ; CHECK-NEXT: ptrue p0.d 59 ; CHECK-NEXT: ptrue p0.d 72 ; CHECK-NEXT: ptrue p0.d 90 ; CHECK-NEXT: ptrue p0.s 102 ; CHECK-NEXT: ptrue p0.d 118 ; CHECK-NEXT: ptrue p0.d 130 ; CHECK-NEXT: ptrue p0.d 142 ; CHECK-NEXT: ptrue p0.d [all …]`
D	sve-fixed-length-fp-select.ll	21 ; NO_SVE-NOT: ptrue 43 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]] 44 ; CHECK: ptrue [[PG1:p[0-9]+]].h 63 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]] 64 ; CHECK: ptrue [[PG1:p[0-9]+]].h 83 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]] 84 ; CHECK: ptrue [[PG1:p[0-9]+]].h 103 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]] 104 ; CHECK: ptrue [[PG1:p[0-9]+]].h 141 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]] [all …]
D	sve-fixed-length-fp-rounding.ll	`21 ; NO_SVE-NOT: ptrue 47 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 60 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 67 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16 84 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 97 ; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 128 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 141 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 148 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8 165 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 [all …]`
D	sve-split-int-reduce.ll	`13 ; CHECK-NEXT: ptrue p0.h 25 ; CHECK-NEXT: ptrue p0.s 38 ; CHECK-NEXT: ptrue p0.d 53 ; CHECK-NEXT: ptrue p0.d 66 ; CHECK-NEXT: ptrue p0.d 79 ; CHECK-NEXT: ptrue p0.s 92 ; CHECK-NEXT: ptrue p0.s 105 ; CHECK-NEXT: ptrue p0.h 120 ; CHECK-NEXT: ptrue p0.s 134 ; CHECK-NEXT: ptrue p0.d [all …]`
D	sve-fixed-length-trunc.ll	`29 ; CHECK: ptrue [[PG:p[0-9]+]].h, vl16 41 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32 55 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64 69 ; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128 86 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 98 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 111 ; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32 126 ; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64 144 ; CHECK: ptrue [[PG:p[0-9]+]].s, vl8 156 ; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16 [all …]`
D	sve-fixed-length-int-immediates.ll	`17 ; CHECK-NEXT: ptrue p0.b, vl64 34 ; CHECK-NEXT: ptrue p0.h, vl32 51 ; CHECK-NEXT: ptrue p0.s, vl16 68 ; CHECK-NEXT: ptrue p0.d, vl8 89 ; CHECK-NEXT: ptrue p0.b, vl64 105 ; CHECK-NEXT: ptrue p0.h, vl32 121 ; CHECK-NEXT: ptrue p0.s, vl16 137 ; CHECK-NEXT: ptrue p0.d, vl8 157 ; CHECK-NEXT: ptrue p0.b, vl64 173 ; CHECK-NEXT: ptrue p0.h, vl32 [all …]`

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