/external/arm-trusted-firmware/plat/xilinx/versal/ |
D | plat_psci.c | 58 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend() 62 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend() 66 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in versal_pwr_domain_suspend() 73 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend() 93 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_suspend_finish() 102 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in versal_pwr_domain_suspend_finish() 158 __func__, i, target_state->pwr_domain_state[i]); in versal_pwr_domain_off() 194 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state() 196 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state() 212 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state() [all …]
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/external/arm-trusted-firmware/plat/xilinx/zynqmp/ |
D | plat_psci.c | 59 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_off() 83 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend() 85 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? in zynqmp_pwr_domain_suspend() 92 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend() 102 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_on_finish() 114 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend_finish() 122 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { in zynqmp_pwr_domain_suspend_finish() 171 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state() 173 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state() 192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state() [all …]
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/external/arm-trusted-firmware/plat/arm/board/fvp/ |
D | fvp_pm.c | 106 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_power_domain_on_finish_common() 113 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_power_domain_on_finish_common() 130 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == in fvp_power_domain_on_finish_common() 186 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_off() 204 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_pwr_domain_off() 222 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend() 226 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend() 245 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == in fvp_pwr_domain_suspend() 250 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == in fvp_pwr_domain_suspend() 295 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == in fvp_pwr_domain_suspend_finish() [all …]
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/external/arm-trusted-firmware/plat/rockchip/common/ |
D | plat_pm.c | 22 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 24 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 153 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state() 157 req_state->pwr_domain_state[i] = in rockchip_validate_power_state() 161 req_state->pwr_domain_state[i] = in rockchip_validate_power_state() 177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state() 232 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_off() 268 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_suspend() 289 lvl_state = target_state->pwr_domain_state[lvl]; in rockchip_pwr_domain_on_finish() [all …]
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/ |
D | plat_psci_handlers.c | 55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state() 64 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; in tegra_soc_validate_power_state() 65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state() 82 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in tegra_soc_validate_power_state() 84 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = in tegra_soc_validate_power_state() 197 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_suspend() local 198 target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend() 199 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; in tegra_soc_pwr_domain_suspend() 200 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; in tegra_soc_pwr_domain_suspend() 201 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_suspend() [all …]
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/external/arm-trusted-firmware/plat/imx/common/ |
D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state() 45 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; in imx_validate_power_state() 47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state() 59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state() 60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/qti/common/src/ |
D | qti_pm.c | 105 req_state->pwr_domain_state[i++] = state_id & in qti_validate_power_state() 146 if ((target_state->pwr_domain_state[QTI_PWR_LVL0] == in is_cpu_off() 148 (target_state->pwr_domain_state[QTI_PWR_LVL0] == in is_cpu_off() 159 (const uint8_t *)target_state->pwr_domain_state; in qti_cpu_power_on_finish() 174 target_state->pwr_domain_state); in qti_node_power_off() 184 pwr_domain_state); in qti_node_suspend() 194 (const uint8_t *)target_state->pwr_domain_state; in qti_node_suspend_finish() 246 req_state->pwr_domain_state[i++] = in qti_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/mediatek/mt8173/ |
D | plat_pm.c | 37 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] 38 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] 40 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0) 376 assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF); in plat_power_domain_on_finish() 379 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) in plat_power_domain_on_finish() 382 if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) { in plat_power_domain_on_finish() 388 (state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF)) in plat_power_domain_on_finish() 406 if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET) in plat_power_domain_suspend_finish() 439 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_get_sys_suspend_power_state() 490 req_state->pwr_domain_state[MTK_PWR_LVL0] = in plat_validate_power_state() [all …]
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/ |
D | plat_psci_handlers.c | 81 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state() 82 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; in tegra_soc_validate_power_state() 103 const plat_local_state_t *pwr_domain_state; in tegra_soc_pwr_domain_suspend() local 112 pwr_domain_state = target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend() 113 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & in tegra_soc_pwr_domain_suspend() 115 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_suspend() 281 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local 282 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi() 284 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_power_down_wfi() 372 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; in tegra_soc_pwr_domain_on_finish() [all …]
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/external/arm-trusted-firmware/plat/intel/soc/common/ |
D | socfpga_psci.c | 62 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_off() 78 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend() 94 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_on_finish() 117 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend_finish() 192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state() 193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/renesas/common/ |
D | plat_pm.c | 35 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 36 #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1]) 37 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0]) 252 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state() 255 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state() 274 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state() 279 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state() 281 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in rcar_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/ |
D | plat_psci_handlers.c | 82 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in tegra_soc_validate_power_state() 83 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN; in tegra_soc_validate_power_state() 116 const plat_local_state_t *pwr_domain_state; in tegra_soc_pwr_domain_suspend() local 131 pwr_domain_state = target_state->pwr_domain_state; in tegra_soc_pwr_domain_suspend() 132 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_suspend() 265 const plat_local_state_t *pwr_domain_state = in tegra_soc_pwr_domain_power_down_wfi() local 266 target_state->pwr_domain_state; in tegra_soc_pwr_domain_power_down_wfi() 268 uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & in tegra_soc_pwr_domain_power_down_wfi() 348 uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; in tegra_soc_pwr_domain_on_finish()
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/external/arm-trusted-firmware/plat/allwinner/common/ |
D | sunxi_pm.c | 34 ((state)->pwr_domain_state[CPU_PWR_LVL]) 36 ((state)->pwr_domain_state[CLUSTER_PWR_LVL]) 38 ((state)->pwr_domain_state[SYSTEM_PWR_LVL]) 192 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; in sunxi_validate_power_state() 198 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_validate_power_state() 202 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; in sunxi_validate_power_state() 222 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/mediatek/mt8183/ |
D | plat_pm.c | 81 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] 82 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] 84 (state)->pwr_domain_state[MTK_PWR_LVL2] : 0) 331 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_off() 350 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_on_finish() 366 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_suspend() 406 const plat_local_state_t *pds = state->pwr_domain_state; in plat_mtk_power_domain_suspend_finish() 471 req_state->pwr_domain_state[i++] = state_id & in plat_mtk_validate_power_state() 502 req_state->pwr_domain_state[MTK_PWR_LVL0] = MTK_LOCAL_STATE_RET; in plat_mtk_validate_power_state() 507 req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF; in plat_mtk_validate_power_state() [all …]
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/external/arm-trusted-firmware/plat/hisilicon/hikey/ |
D | hikey_pm.c | 24 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 26 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 28 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 168 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey_get_sys_suspend_power_state() 235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state() 239 req_state->pwr_domain_state[i] = in hikey_validate_power_state()
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/external/arm-trusted-firmware/plat/imx/imx8m/include/ |
D | imx8m_psci.h | 10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 12 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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/external/arm-trusted-firmware/plat/mediatek/mt8192/include/ |
D | plat_pm.h | 28 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER]) 30 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS]) 32 is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
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/external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
D | hikey960_pm.c | 27 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 29 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 31 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 159 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state() 163 req_state->pwr_domain_state[i] = in hikey960_validate_power_state() 294 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey960_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/imx/imx8qx/ |
D | imx8qx_psci.c | 116 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) { in imx_domain_suspend() 127 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend() 130 if (is_local_state_retn(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL])) { in imx_domain_suspend() 169 if (is_local_state_retn(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL])) { in imx_domain_suspend_finish() 203 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1])) in imx_domain_suspend_finish() 206 if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) { in imx_domain_suspend_finish()
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/external/arm-trusted-firmware/lib/psci/ |
D | psci_common.c | 309 plat_local_state_t *pd_state = target_state->pwr_domain_state; in psci_get_target_local_pwr_states() 322 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; in psci_get_target_local_pwr_states() 335 const plat_local_state_t *pd_state = target_state->pwr_domain_state; in psci_set_target_local_pwr_states() 437 state_info->pwr_domain_state[lvl]); in psci_do_state_coordination() 452 state_info->pwr_domain_state[lvl] = target_state; in psci_do_state_coordination() 455 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) in psci_do_state_coordination() 469 state_info->pwr_domain_state[lvl]); in psci_do_state_coordination() 470 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; in psci_do_state_coordination() 506 state = state_info->pwr_domain_state[i]; in psci_validate_suspend_req() 551 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) in psci_find_max_off_lvl() [all …]
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/external/arm-trusted-firmware/plat/amlogic/axg/ |
D | axg_pm.c | 102 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_on_finish() 117 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_off() 124 if (target_state->pwr_domain_state[MPIDR_AFFLVL2] == in axg_pwr_domain_off() 128 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == in axg_pwr_domain_off()
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/external/arm-trusted-firmware/include/plat/arm/css/common/ |
D | css_pm.h | 16 #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] 17 #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] 22 return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; in css_system_pwr_state()
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/external/arm-trusted-firmware/plat/hisilicon/poplar/ |
D | plat_pm.c | 76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in poplar_pwr_domain_on_finish() 120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state() 122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state() 148 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in poplar_get_sys_suspend_power_state()
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/external/arm-trusted-firmware/plat/brcm/board/stingray/src/ |
D | brcm_pm_ops.c | 28 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 30 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 31 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL2]) 364 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in brcm_validate_power_state() 368 req_state->pwr_domain_state[i] = in brcm_validate_power_state()
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/external/arm-trusted-firmware/drivers/arm/css/scp/ |
D | css_pm_scmi.c | 113 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in css_scp_suspend() 143 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) in css_scp_suspend() 146 assert(target_state->pwr_domain_state[lvl] == in css_scp_suspend() 182 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == in css_scp_off() 189 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN) in css_scp_off() 192 assert(target_state->pwr_domain_state[lvl] == in css_scp_off()
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