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Searched refs:qadd (Results 1 – 25 of 53) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/
Ddsp-loop-indexing.ll38 %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
40 store i32 %qadd.1, i32* %addr.1
46 %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2)
48 store i32 %qadd.2, i32* %addr.2
93 %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
95 store i32 %qadd.1, i32* %addr.1
101 %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2)
103 store i32 %qadd.2, i32* %addr.2
147 %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1)
149 store i32 %qadd.1, i32* %addr.1
[all …]
Dacle-intrinsics-v5.ll67 define i32 @qadd(i32 %a, i32 %b) nounwind {
68 ; CHECK-LABEL: qadd
69 ; CHECK: qadd r0, r0, r1
70 %tmp = call i32 @llvm.arm.qadd(i32 %a, i32 %b)
84 %dbl = call i32 @llvm.arm.qadd(i32 %a, i32 %a)
85 %add = call i32 @llvm.arm.qadd(i32 %dbl, i32 %b)
92 %dbl = call i32 @llvm.arm.qadd(i32 %b, i32 %b)
109 declare i32 @llvm.arm.qadd(i32, i32) nounwind
Dsadd_sat.ll65 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
83 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
88 ; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
292 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
353 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
399 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
416 ; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
424 ; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
Dsadd_sat_plus.ll65 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
71 ; CHECK-ARM-NEXT: qadd r0, r0, r1
364 ; CHECK-T2DSP-NEXT: qadd r0, r0, r1
373 ; CHECK-ARM-NEXT: qadd r0, r0, r1
Dqdadd.ll171 ; CHECK-T2DSP-NEXT: qadd r0, r0, r0
177 ; CHECK-ARM-NEXT: qadd r0, r0, r0
/external/llvm/test/CodeGen/ARM/
Dsat-arith.ll4 ; CHECK-LABEL: qadd
5 define i32 @qadd() nounwind {
8 ; CHECK-ARM: qadd [[R0]], [[R1]], [[R0]]
9 ; CHECK-THRUMB: qadd [[R0]], [[R0]], [[R1]]
10 %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
19 ; CHECK-THRUMB: qadd [[R0]], [[R1]], [[R0]]
60 declare i32 @llvm.arm.qadd(i32, i32) nounwind
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvqaddq.ll50 …%2 = tail call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32…
56 declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <…
68 …%2 = tail call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 …
74 declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 …
86 …%2 = tail call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 …
92 declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 …
142 …%2 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, i32…
158 …%2 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, i32 …
174 …%2 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, i32 …
/external/llvm-project/llvm/test/MC/ARM/
Dinvalid-instructions-spellcheck.s34 @ and 'qadd' a distance of 2 (a deletion and an insertion)
57 @ For example, in Thumb mode we don't want to see suggestions 'faddd' of 'qadd'
/external/arm-neon-tests/
Dref_dsp.c61 sres = qadd(svar1, svar2); in exec_dsp()
67 sres = qadd(svar1, svar2); in exec_dsp()
73 sres = qadd(svar1, svar2); in exec_dsp()
79 sres = qadd(svar1, svar2); in exec_dsp()
85 sres = qadd(svar1, svar2); in exec_dsp()
91 sres = qadd(svar1, svar2); in exec_dsp()
97 sres = qadd(svar1, svar2); in exec_dsp()
Dref-rvct-all.txt7973 qadd(0x1, 0x2) = 0x3 sat 0
7974 qadd(0xffffffff, 0xfffffffe) = 0xfffffffd sat 0
7975 qadd(0xffffffff, 0x2) = 0x1 sat 0
7976 qadd(0x7000, 0x7000) = 0xe000 sat 0
7977 qadd(0x8fff, 0x8fff) = 0x11ffe sat 0
7978 qadd(0x70000000, 0x70000000) = 0x7fffffff sat 1
7979 qadd(0x8fffffff, 0x8fffffff) = 0x80000000 sat 1
/external/boringssl/src/crypto/fipsmodule/bn/
Dprime.c996 BIGNUM *t1, *qadd, *q; in probable_prime_dh_safe() local
1002 qadd = BN_CTX_get(ctx); in probable_prime_dh_safe()
1003 if (qadd == NULL) { in probable_prime_dh_safe()
1007 if (!BN_rshift1(qadd, padd)) { in probable_prime_dh_safe()
1016 if (!BN_mod(t1, q, qadd, ctx)) { in probable_prime_dh_safe()
1056 if (!BN_add(q, q, qadd)) { in probable_prime_dh_safe()
/external/rust/crates/quiche/deps/boringssl/src/crypto/fipsmodule/bn/
Dprime.c996 BIGNUM *t1, *qadd, *q; in probable_prime_dh_safe() local
1002 qadd = BN_CTX_get(ctx); in probable_prime_dh_safe()
1003 if (qadd == NULL) { in probable_prime_dh_safe()
1007 if (!BN_rshift1(qadd, padd)) { in probable_prime_dh_safe()
1016 if (!BN_mod(t1, q, qadd, ctx)) { in probable_prime_dh_safe()
1056 if (!BN_add(q, q, qadd)) { in probable_prime_dh_safe()
/external/libopus/m4/
Das-gcc-inline-assembly.m482 AC_COMPILE_IFELSE([AC_LANG_PROGRAM([],[__asm__("qadd r3,r3,r3")])],
/external/llvm-project/clang/test/Driver/
Darmv8.1m.main.s34 qadd r0, r1, r2 label
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dunpredload.ll35 …%6 = tail call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %4, <8 x i16> %5, i32 …
180 declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 …
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc105 M(qadd) \
Dtest-assembler-cond-rd-rn-rm-a32.cc106 M(qadd) \
/external/libopus/
Dmeson.build229 if cc.compiles(asm_tmpl.format('qadd r3,r3,r3'),
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s208 qadd r0, r1, r2 label
640 # CHECK-NEXT: 1 2 1.00 qadd r0, r1, r2
1080 …0.50 - - - - 1.00 - - - - - - qadd r0, r1, r2
Dm4-int.s215 qadd r0, r1, r2 label
662 # CHECK-NEXT: 1 1 1.00 qadd r0, r1, r2
1100 # CHECK-NEXT: 1.00 qadd r0, r1, r2
Dcortex-a57-basic-instructions.s416 qadd r1, r2, r3
1286 # CHECK-NEXT: 1 2 1.00 U qadd r1, r2, r3
2163 # CHECK-NEXT: - - - - 1.00 - - - qadd r1, r2, r3
Dcortex-a57-thumb.s476 qadd r1, r2, r3
1384 # CHECK-NEXT: 1 2 1.00 qadd r1, r2, r3
2298 # CHECK-NEXT: - - - - 1.00 - - - qadd r1, r2, r3
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-qrintr.ll169 …%3 = tail call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %2, <4 x i32> %.splat,…
680 declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 …
/external/llvm-project/llvm/test/Transforms/HardwareLoops/ARM/
Dcalls.ll290 ; TODO: We should be able to generate a qadd/sub
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs490 0x52,0x10,0x03,0xe1 = qadd r1, r2, r3

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