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Searched refs:qdsub (Results 1 – 25 of 33) sorted by relevance

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/external/arm-neon-tests/
Dref_dsp.c212 sres = qdsub(svar1, svar2); in exec_dsp()
218 sres = qdsub(svar1, svar2); in exec_dsp()
224 sres = qdsub(svar1, svar2); in exec_dsp()
230 sres = qdsub(svar1, svar2); in exec_dsp()
236 sres = qdsub(svar1, svar2); in exec_dsp()
242 sres = qdsub(svar1, svar2); in exec_dsp()
248 sres = qdsub(svar1, svar2); in exec_dsp()
254 sres = qdsub(svar1, svar2); in exec_dsp()
260 sres = qdsub(svar1, svar2); in exec_dsp()
Dref-rvct-all.txt7997 qdsub(0x1, 0x2) = 0xfffffffd sat 0
7998 qdsub(0xffffffff, 0xfffffffe) = 0x3 sat 0
7999 qdsub(0xffffffff, 0x2) = 0xfffffffb sat 0
8000 qdsub(0x7000, 0xffff9000) = 0x15000 sat 0
8001 qdsub(0x8fff, 0xffff7001) = 0x1affd sat 0
8002 qdsub(0x70000000, 0x90000000) = 0x7fffffff sat 1
8003 qdsub(0, 0x90000000) = 0x7fffffff sat 1
8004 qdsub(0x8fffffff, 0x70000001) = 0x80000000 sat 1
8005 qdsub(0, 0x70000001) = 0x80000001 sat 1
/external/llvm-project/llvm/test/CodeGen/ARM/
Dqdadd.ll95 define i32 @qdsub(i32 %x, i32 %y) nounwind {
96 ; CHECK-T2NODSP-LABEL: qdsub:
125 ; CHECK-T2DSP-LABEL: qdsub:
127 ; CHECK-T2DSP-NEXT: qdsub r0, r1, r0
130 ; CHECK-ARM-LABEL: qdsub:
132 ; CHECK-ARM-NEXT: qdsub r0, r1, r0
Dacle-intrinsics-v5.ll89 define i32 @qdsub(i32 %a, i32 %b) nounwind {
90 ; CHECK-LABEL: qdsub
91 ; CHECK: qdsub r0, r0, r1
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-rn-rm-t32.cc107 M(qdsub) \
Dtest-assembler-cond-rd-rn-rm-a32.cc108 M(qdsub) \
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-int.s213 qdsub r0, r1, r2 label
645 # CHECK-NEXT: 1 3 1.00 qdsub r0, r1, r2
1085 ….50 - - - - 1.00 1.00 - - - - - qdsub r0, r1, r2
Dm4-int.s220 qdsub r0, r1, r2 label
667 # CHECK-NEXT: 1 1 1.00 qdsub r0, r1, r2
1105 # CHECK-NEXT: 1.00 qdsub r0, r1, r2
Dcortex-a57-basic-instructions.s424 qdsub r6, r7, r8
1294 # CHECK-NEXT: 2 3 1.00 U qdsub r6, r7, r8
2171 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qdsub r6, r7, r8
Dcortex-a57-thumb.s484 qdsub r6, r7, r8
1392 # CHECK-NEXT: 2 3 1.00 qdsub r6, r7, r8
2306 # CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qdsub r6, r7, r8
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs498 0x57,0x60,0x68,0xe1 = qdsub r6, r7, r8
/external/vixl/src/aarch32/
Dassembler-aarch32.h2839 void qdsub(Condition cond, Register rd, Register rm, Register rn);
2840 void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); } in qdsub() function
Ddisasm-aarch32.h998 void qdsub(Condition cond, Register rd, Register rm, Register rn);
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1837 qdsub r6, r7, r8
1842 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x57,0x60,0x68,0xe1]
Dbasic-thumb2-instructions.s2084 qdsub r6, r7, r8
2090 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1807 qdsub r6, r7, r8
1812 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x57,0x60,0x68,0xe1]
Dbasic-thumb2-instructions.s1875 qdsub r6, r7, r8
1881 @ CHECK: qdsub r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt1153 # CHECK: qdsub r6, r7, r8
Dthumb2.txt1387 # CHECK: qdsub r6, r7, r8
/external/llvm/test/MC/Disassembler/ARM/
Dthumb2.txt1387 # CHECK: qdsub r6, r7, r8
Dbasic-arm-instructions.txt1153 # CHECK: qdsub r6, r7, r8
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc580 { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */
5860 { /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc580 { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */
5860 { /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td2143 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td2433 def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">;

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