/external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
D | qmdc3c0.c | 30 NVC3C0QmdDump_V02_02(uint32_t *qmd) in NVC3C0QmdDump_V02_02() argument 32 NVC3C0_QMDV02_02_VAL(qmd, OUTER_PUT, "0x%x"); in NVC3C0QmdDump_V02_02() 33 NVC3C0_QMDV02_02_VAL(qmd, OUTER_OVERFLOW, "0x%x"); in NVC3C0QmdDump_V02_02() 34 NVC3C0_QMDV02_02_VAL(qmd, OUTER_GET, "0x%x"); in NVC3C0QmdDump_V02_02() 35 NVC3C0_QMDV02_02_VAL(qmd, OUTER_STICKY_OVERFLOW, "0x%x"); in NVC3C0QmdDump_V02_02() 36 NVC3C0_QMDV02_02_VAL(qmd, INNER_GET, "0x%x"); in NVC3C0QmdDump_V02_02() 37 NVC3C0_QMDV02_02_VAL(qmd, INNER_OVERFLOW, "0x%x"); in NVC3C0QmdDump_V02_02() 38 NVC3C0_QMDV02_02_VAL(qmd, INNER_PUT, "0x%x"); in NVC3C0QmdDump_V02_02() 39 NVC3C0_QMDV02_02_VAL(qmd, INNER_STICKY_OVERFLOW, "0x%x"); in NVC3C0QmdDump_V02_02() 40 NVC3C0_QMDV02_02_VAL(qmd, QMD_GROUP_ID, "0x%x"); in NVC3C0QmdDump_V02_02() [all …]
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D | qmdc0c0.c | 30 NVC0C0QmdDump_V02_01(uint32_t *qmd) in NVC0C0QmdDump_V02_01() argument 32 NVC0C0_QMDV02_01_VAL(qmd, OUTER_PUT, "0x%x"); in NVC0C0QmdDump_V02_01() 33 NVC0C0_QMDV02_01_VAL(qmd, OUTER_OVERFLOW, "0x%x"); in NVC0C0QmdDump_V02_01() 34 NVC0C0_QMDV02_01_VAL(qmd, OUTER_GET, "0x%x"); in NVC0C0QmdDump_V02_01() 35 NVC0C0_QMDV02_01_VAL(qmd, OUTER_STICKY_OVERFLOW, "0x%x"); in NVC0C0QmdDump_V02_01() 36 NVC0C0_QMDV02_01_VAL(qmd, INNER_GET, "0x%x"); in NVC0C0QmdDump_V02_01() 37 NVC0C0_QMDV02_01_VAL(qmd, INNER_OVERFLOW, "0x%x"); in NVC0C0QmdDump_V02_01() 38 NVC0C0_QMDV02_01_VAL(qmd, INNER_PUT, "0x%x"); in NVC0C0QmdDump_V02_01() 39 NVC0C0_QMDV02_01_VAL(qmd, INNER_STICKY_OVERFLOW, "0x%x"); in NVC0C0QmdDump_V02_01() 40 NVC0C0_QMDV02_01_VAL(qmd, QMD_GROUP_ID, "0x%x"); in NVC0C0QmdDump_V02_01() [all …]
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D | qmda0c0.c | 30 NVA0C0QmdDump_V00_06(uint32_t *qmd) in NVA0C0QmdDump_V00_06() argument 32 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_A, "0x%x"); in NVA0C0QmdDump_V00_06() 33 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_B, "0x%x"); in NVA0C0QmdDump_V00_06() 34 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_C, "0x%x"); in NVA0C0QmdDump_V00_06() 35 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_D, "0x%x"); in NVA0C0QmdDump_V00_06() 36 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_E, "0x%x"); in NVA0C0QmdDump_V00_06() 37 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_F, "0x%x"); in NVA0C0QmdDump_V00_06() 38 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_G, "0x%x"); in NVA0C0QmdDump_V00_06() 39 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_H, "0x%x"); in NVA0C0QmdDump_V00_06() 40 NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_A_A, "0x%x"); in NVA0C0QmdDump_V00_06() [all …]
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D | nve4_compute.c | 570 gp100_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index, in gp100_cp_launch_desc_set_cb() argument 578 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address); in gp100_cp_launch_desc_set_cb() 579 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32); in gp100_cp_launch_desc_set_cb() 580 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, index, in gp100_cp_launch_desc_set_cb() 582 NVC0C0_QMDV02_01_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE); in gp100_cp_launch_desc_set_cb() 586 nve4_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index, struct nouveau_bo *bo, in nve4_cp_launch_desc_set_cb() argument 594 NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address); in nve4_cp_launch_desc_set_cb() 595 NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32); in nve4_cp_launch_desc_set_cb() 596 NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_SIZE, index, size); in nve4_cp_launch_desc_set_cb() 597 NVA0C0_QMDV00_06_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE); in nve4_cp_launch_desc_set_cb() [all …]
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/external/mesa3d/src/gallium/drivers/nouveau/ |
D | Makefile.sources | 165 nvc0/qmd.h \
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D | meson.build | 175 'nvc0/qmd.h',
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