/external/mesa3d/src/broadcom/compiler/ |
D | vir_opt_redundant_flags.c | 45 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU); in vir_dce_pf() 47 inst->qpu.flags.apf = V3D_QPU_PF_NONE; in vir_dce_pf() 48 inst->qpu.flags.mpf = V3D_QPU_PF_NONE; in vir_dce_pf() 80 if (a->qpu.flags.apf != b->qpu.flags.apf || in vir_instr_flags_op_equal() 81 a->qpu.flags.mpf != b->qpu.flags.mpf || in vir_instr_flags_op_equal() 82 a->qpu.alu.add.op != b->qpu.alu.add.op || in vir_instr_flags_op_equal() 83 a->qpu.alu.mul.op != b->qpu.alu.mul.op || in vir_instr_flags_op_equal() 84 a->qpu.alu.add.a_unpack != b->qpu.alu.add.a_unpack || in vir_instr_flags_op_equal() 85 a->qpu.alu.add.b_unpack != b->qpu.alu.add.b_unpack || in vir_instr_flags_op_equal() 86 a->qpu.alu.add.output_pack != b->qpu.alu.add.output_pack || in vir_instr_flags_op_equal() [all …]
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D | vir_to_qpu.c | 143 if (qinst->qpu.type != V3D_QPU_INSTR_TYPE_ALU || in is_no_op_mov() 144 qinst->qpu.alu.mul.op != V3D_QPU_M_MOV || in is_no_op_mov() 145 qinst->qpu.alu.add.op != V3D_QPU_A_NOP || in is_no_op_mov() 146 memcmp(&qinst->qpu.sig, &no_sig, sizeof(no_sig)) != 0) { in is_no_op_mov() 151 enum v3d_qpu_waddr waddr = qinst->qpu.alu.mul.waddr; in is_no_op_mov() 152 if (qinst->qpu.alu.mul.magic_write) { in is_no_op_mov() 156 if (qinst->qpu.alu.mul.a != in is_no_op_mov() 163 switch (qinst->qpu.alu.mul.a) { in is_no_op_mov() 165 raddr = qinst->qpu.raddr_a; in is_no_op_mov() 168 raddr = qinst->qpu.raddr_b; in is_no_op_mov() [all …]
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D | vir_opt_copy_propagate.c | 43 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU || in is_copy_mov() 44 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV && in is_copy_mov() 45 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) { in is_copy_mov() 55 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE || in is_copy_mov() 56 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) { in is_copy_mov() 60 if (inst->qpu.flags.ac != V3D_QPU_COND_NONE || in is_copy_mov() 61 inst->qpu.flags.mc != V3D_QPU_COND_NONE) { in is_copy_mov() 107 return inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack() 109 return inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack() 112 return inst->qpu.alu.mul.a_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack() [all …]
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D | vir_opt_dead_code.c | 50 assert(!v3d_qpu_writes_flags(&inst->qpu)); in dce() 69 if (c->devinfo->ver >= 41 && v3d_qpu_uses_sfu(&inst->qpu)) in can_write_to_null() 85 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU); in vir_dce_flags() 87 inst->qpu.flags.apf = V3D_QPU_PF_NONE; in vir_dce_flags() 88 inst->qpu.flags.mpf = V3D_QPU_PF_NONE; in vir_dce_flags() 89 inst->qpu.flags.auf = V3D_QPU_UF_NONE; in vir_dce_flags() 90 inst->qpu.flags.muf = V3D_QPU_UF_NONE; in vir_dce_flags() 119 if (v3d_qpu_reads_flags(&inst->qpu)) in vir_opt_dead_code() 131 if (v3d_qpu_writes_flags(&inst->qpu)) { in vir_opt_dead_code() 136 (inst->qpu.flags.apf != V3D_QPU_PF_NONE || in vir_opt_dead_code() [all …]
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D | vir.c | 32 switch (inst->qpu.type) { in vir_get_nsrc() 36 if (inst->qpu.alu.add.op != V3D_QPU_A_NOP) in vir_get_nsrc() 37 return v3d_qpu_add_op_num_src(inst->qpu.alu.add.op); in vir_get_nsrc() 39 return v3d_qpu_mul_op_num_src(inst->qpu.alu.mul.op); in vir_get_nsrc() 52 switch (inst->qpu.type) { in vir_has_side_effects() 56 switch (inst->qpu.alu.add.op) { in vir_has_side_effects() 70 switch (inst->qpu.alu.mul.op) { in vir_has_side_effects() 78 if (inst->qpu.sig.ldtmu || in vir_has_side_effects() 79 inst->qpu.sig.ldvary || in vir_has_side_effects() 80 inst->qpu.sig.ldtlbu || in vir_has_side_effects() [all …]
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D | vir_dump.c | 173 inst->qpu.raddr_b, in vir_print_reg() 177 if ((int)inst->qpu.raddr_b >= -16 && in vir_print_reg() 178 (int)inst->qpu.raddr_b <= 15) in vir_print_reg() 217 struct v3d_qpu_sig *sig = &inst->qpu.sig; in vir_dump_sig() 223 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig() 229 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig() 233 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig() 237 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig() 243 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig() 249 vir_dump_sig_addr(c->devinfo, &inst->qpu); in vir_dump_sig() [all …]
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D | vir_opt_small_immediates.c | 41 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU) in vir_opt_small_immediates() 63 if (!src_def || !src_def->qpu.sig.ldunif) in vir_opt_small_immediates() 81 struct v3d_qpu_sig new_sig = inst->qpu.sig; in vir_opt_small_immediates() 92 inst->qpu.sig.small_imm = true; in vir_opt_small_immediates() 93 inst->qpu.raddr_b = packed; in vir_opt_small_immediates()
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D | vir_register_allocate.c | 41 inst->qpu.sig.wrtmuc; in qinst_writes_tmu() 47 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && in is_end_of_tmu_sequence() 48 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) in is_end_of_tmu_sequence() 51 if (!inst->qpu.sig.ldtmu) in is_end_of_tmu_sequence() 56 if (scan_inst->qpu.sig.ldtmu) in is_end_of_tmu_sequence() 70 return def && def->qpu.sig.ldunif; in vir_is_mov_uniform() 133 if (inst->qpu.sig.ldvary) { in v3d_choose_spill_node() 141 if (v3d_qpu_writes_vpm(&inst->qpu) || in v3d_choose_spill_node() 142 v3d_qpu_uses_tlb(&inst->qpu)) in v3d_choose_spill_node() 334 (v3d_qpu_writes_vpm(&inst->qpu) || in v3d_spill_reg() [all …]
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D | qpu_schedule.c | 156 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n); in process_mux_deps() 159 if (!n->inst->qpu.sig.small_imm) { in process_mux_deps() 161 state->last_rf[n->inst->qpu.raddr_b], n); in process_mux_deps() 251 struct v3d_qpu_instr *inst = &qinst->qpu; in calculate_deps() 476 const struct v3d_qpu_instr *inst = &qinst->qpu; in reads_too_soon_after_write() 516 const struct v3d_qpu_instr *inst = &qinst->qpu; in writes_too_soon_after_write() 770 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule() 776 const struct v3d_qpu_instr *inst = &n->inst->qpu; in choose_instruction_to_schedule() 845 &prev_inst->inst->qpu, inst)) { in choose_instruction_to_schedule() 947 v3d_qpu_dump(devinfo, &n->inst->qpu); in dump_state() [all …]
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D | vir_live_variables.c | 86 if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU) in vir_setup_def() 110 if ((inst->qpu.flags.ac == V3D_QPU_COND_NONE && in vir_setup_def() 111 inst->qpu.flags.mc == V3D_QPU_COND_NONE) && in vir_setup_def() 112 inst->qpu.alu.add.output_pack == V3D_QPU_PACK_NONE && in vir_setup_def() 113 inst->qpu.alu.mul.output_pack == V3D_QPU_PACK_NONE) { in vir_setup_def() 140 if (inst->qpu.flags.ac == V3D_QPU_COND_NONE && in vir_setup_def() 141 inst->qpu.flags.mc == V3D_QPU_COND_NONE) { in vir_setup_def() 170 (state->insts[i]->qpu.flags.ac != V3D_QPU_COND_NONE || in sf_state_clear() 171 state->insts[i]->qpu.flags.mc != V3D_QPU_COND_NONE)) in sf_state_clear()
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D | qpu_validate.c | 65 v3d_qpu_dump(c->devinfo, &inst->qpu); in fail_instr() 113 const struct v3d_qpu_instr *inst = &qinst->qpu; in qpu_validate_inst() 287 state->last = &qinst->qpu; in qpu_validate_block()
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D | v3d_compiler.h | 134 struct v3d_qpu_instr qpu; member 1206 ldtmu->qpu.sig.ldtmu = true; in vir_LDTMU() 1210 vir_NOP(c)->qpu.sig.ldtmu = true; in vir_LDTMU() 1230 ldtlb->qpu.sig.ldtlbu = true; in vir_TLBU_COLOR_READ() 1242 ldtlb->qpu.sig.ldtlb = true; in vir_TLB_COLOR_READ()
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D | v3d40_tex.c | 49 inst->qpu.sig.wrtmuc = true; in vir_WRTMUC()
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D | nir_to_vir.c | 131 c->last_thrsw->qpu.sig.thrsw = true; in vir_emit_thrsw() 508 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) { in ntq_store_dest() 700 ldvary->qpu.sig.ldvary = true; in emit_fragment_varying() 703 vir_NOP(c)->qpu.sig.ldvary = true; in emit_fragment_varying() 3055 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P; in ntq_emit_loop() 3270 if (inst->qpu.sig.thrsw) in vir_remove_thrsw()
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/external/mesa3d/src/broadcom/ |
D | Makefile.sources | 47 qpu/qpu_disasm.c \ 48 qpu/qpu_disasm.h \ 49 qpu/qpu_instr.c \ 50 qpu/qpu_instr.h \ 51 qpu/qpu_pack.c \
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D | meson.build | 30 subdir('qpu') subdir
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/external/mesa3d/docs/relnotes/ |
D | 18.0.0.rst | 217 - mesa-17.3.0/src/broadcom/qpu/qpu_pack.c:171]: (error) Invalid
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D | 20.1.0.rst | 234 - src/broadcom/qpu/qpu_pack.c:962:25: error: implicit declaration of
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D | 19.1.0.rst | 1412 - v3d: Add support for vir-to-qpu of ldunif instructions to a temp.
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D | 20.2.0.rst | 3647 - broadcom/qpu: set VC5_QPU_RADDR_A out of the switch at _pack_branch
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/external/mesa3d/docs/ |
D | envvars.rst | 517 ``qpu``
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