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Searched refs:qreg (Results 1 – 25 of 26) sorted by relevance

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/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qir.h91 struct qreg { struct
97 static inline struct qreg qir_reg(enum qfile file, uint32_t index) in qir_reg() argument
99 return (struct qreg){file, index}; in qir_reg()
200 struct qreg dst;
201 struct qreg src[3];
410 struct qreg *inputs;
411 struct qreg *outputs;
413 struct qreg color_reads[VC4_MAX_SAMPLES];
414 struct qreg sample_colors[VC4_MAX_SAMPLES];
422 struct qreg execute;
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Dvc4_program.c43 static struct qreg
56 struct qreg **regs, in resize_qreg_array()
65 *regs = reralloc(c, *regs, struct qreg, *size); in resize_qreg_array()
92 static struct qreg
95 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load()
115 static struct qreg
122 struct qreg offset = ntq_get_src(c, intr->src[1], 0); in vc4_ubo_load()
160 static struct qreg *
163 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg, in ntq_init_ssa_def()
186 struct qreg result) in ntq_store_dest()
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Dvc4_qir.c392 qir_print_reg(struct vc4_compile *c, struct qreg reg, bool write) in qir_print_reg()
566 struct qreg
569 struct qreg reg; in qir_get_temp()
588 qir_inst(enum qop op, struct qreg dst, struct qreg src0, struct qreg src1) in qir_inst()
608 struct qreg
635 qir_reg_equals(struct qreg a, struct qreg b) in qir_reg_equals()
718 struct qreg
719 qir_follow_movs(struct vc4_compile *c, struct qreg reg) in qir_follow_movs()
764 struct qreg
797 qir_SF(struct vc4_compile *c, struct qreg src) in qir_SF()
Dvc4_qir_emit_uniform_stream_resets.c58 struct qreg t = qir_get_temp(c); in qir_emit_uniform_stream_resets()
59 struct qreg uni_addr = in qir_emit_uniform_stream_resets()
Dvc4_qir_lower_uniforms.c48 add_uniform(struct hash_table *ht, struct qreg reg) in add_uniform()
62 remove_uniform(struct hash_table *ht, struct qreg reg) in remove_uniform()
148 struct qreg unif = qir_reg(QFILE_UNIF, max_index); in qir_lower_uniforms()
Dvc4_opt_algebraic.c63 is_constant_value(struct vc4_compile *c, struct qreg reg, in is_constant_value()
80 is_zero(struct vc4_compile *c, struct qreg reg) in is_zero()
87 is_1f(struct vc4_compile *c, struct qreg reg) in is_1f()
94 replace_with_mov(struct vc4_compile *c, struct qinst *inst, struct qreg arg) in replace_with_mov()
Dvc4_opt_small_immediates.c67 struct qreg src = qir_follow_movs(c, inst->src[i]); in qir_opt_small_immediates()
Dvc4_opt_constant_folding.c65 struct qreg reg = inst->src[i]; in constant_fold()
Dvc4_qir_live_variables.c38 qir_reg_to_var(struct qreg reg) in qir_reg_to_var()
48 struct qreg src) in qir_setup_use()
Dvc4_opt_peephole_sf.c78 src_file_varies_on_reread(struct qreg reg) in src_file_varies_on_reread()
Dvc4_qir_validate.c109 struct qreg src = inst->src[i]; in qir_validate()
/external/mesa3d/src/broadcom/compiler/
Dv3d_compiler.h95 struct qreg { struct
100 static inline struct qreg vir_reg(enum qfile file, uint32_t index) in vir_reg() argument
102 return (struct qreg){file, index}; in vir_reg()
105 static inline struct qreg vir_magic_reg(uint32_t index) in vir_magic_reg()
107 return (struct qreg){QFILE_MAGIC, index}; in vir_magic_reg()
110 static inline struct qreg vir_nop_reg(void) in vir_nop_reg()
112 return (struct qreg){QFILE_NULL, 0}; in vir_nop_reg()
137 struct qreg dst;
138 struct qreg src[3];
533 struct qreg vp;
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Dnir_to_vir.c76 struct qreg **regs, in resize_qreg_array()
85 *regs = reralloc(c, *regs, struct qreg, *size); in resize_qreg_array()
260 struct qreg base_offset; in ntq_emit_tmu_general()
296 struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD); in ntq_emit_tmu_general()
318 struct qreg tmud = vir_reg(QFILE_MAGIC, in ntq_emit_tmu_general()
321 struct qreg data = in ntq_emit_tmu_general()
337 struct qreg data = in ntq_emit_tmu_general()
386 struct qreg tmua; in ntq_emit_tmu_general()
394 struct qreg offset = base_offset; in ntq_emit_tmu_general()
399 struct qreg data = in ntq_emit_tmu_general()
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Dv3d40_tex.c34 vir_TMU_WRITE(struct v3d_compile *c, enum v3d_qpu_waddr waddr, struct qreg val, in vir_TMU_WRITE()
88 struct qreg s; in v3d40_vir_emit_tex()
153 struct qreg mask = vir_uniform_ui(c, 0xf); in v3d40_vir_emit_tex()
154 struct qreg x, y, offset; in v3d40_vir_emit_tex()
442 struct qreg src[4]; in v3d40_vir_emit_image_load_store()
Dvir.c305 struct qreg
308 struct qreg reg; in vir_get_temp()
333 vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst, struct qreg src0, struct qreg src1) in vir_add_inst()
349 vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst, struct qreg src0, struct qreg src1) in vir_mul_inst()
400 struct qreg
1295 struct qreg
1296 vir_follow_movs(struct v3d_compile *c, struct qreg reg) in vir_follow_movs()
1366 struct qreg
Dv3d33_tex.c71 struct qreg coords[5]; in v3d33_vir_emit_tex()
169 struct qreg dst; in v3d33_vir_emit_tex()
Dvir_live_variables.c37 vir_reg_to_var(struct qreg reg) in vir_reg_to_var()
47 struct qreg src) in vir_setup_use()
Dvir_register_allocate.c183 struct qreg thread_offset = in v3d_setup_spill_base()
189 struct qreg element_offset = vir_SHL(c, vir_EIDX(c), in v3d_setup_spill_base()
291 struct qreg unif = in v3d_spill_reg()
Dvir_dump.c150 struct qreg reg) in vir_print_reg()
Dvir_to_qpu.c79 struct qreg undef = vir_nop_reg(); in vir_nop()
Dqpu_schedule.c1100 struct qreg undef = vir_nop_reg(); in vir_nop()
/external/vixl/test/aarch32/
Dtest-utils-aarch32.cc168 const QRegister& qreg) { in Equal128() argument
170 vec128_t result = core->GetQRegisterBits(qreg.GetCode()); in Equal128()
Dtest-utils-aarch32.h195 const QRegister& qreg);
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h161 inline QRegisterValue qreg(unsigned code) const { return dump_.q_[code]; } in qreg() function
Dtest-utils-aarch64.cc218 QRegisterValue result = core->qreg(vreg.GetCode()); in Equal128()

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