| /external/llvm/test/CodeGen/ARM/ |
| D | sat-arith.ll | 14 ; CHECK-LABEL: qsub
15 define i32 @qsub() nounwind {
18 ; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]]
20 %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
61 declare i32 @llvm.arm.qsub(i32, i32) nounwind
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_esbr_cos_sin_mod_loop2.s | 71 VMULL.S32 q2, d0, d2 @qsub 2nd
74 VMULL.S32 q5, d1, d3 @qsub 1st
102 VMULL.S32 q2, d0, d2 @qsub 2nd
105 VMULL.S32 q5, d1, d3 @qsub 1st
131 VMULL.S32 q2, d0, d2 @qsub 2nd
134 VMULL.S32 q5, d1, d3 @qsub 1st
|
| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 50 VMULL.S32 q2, d0, d2 @qsub 2nd
53 VMULL.S32 q5, d1, d3 @qsub 1st
102 VMULL.S32 q2, d0, d2 @qsub 2nd
105 VMULL.S32 q5, d1, d3 @qsub 1st
|
| /external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
| D | vqsubq.ll | 50 …%2 = tail call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32…
56 declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <…
68 …%2 = tail call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 …
74 declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 …
86 …%2 = tail call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 …
92 declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 …
142 …%2 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, i32…
158 …%2 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %.splat, i32 …
174 …%2 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, i32 …
|
| /external/arm-neon-tests/ |
| D | ref_dsp.c | 105 sres = qsub(svar1, svar2); in exec_dsp()
111 sres = qsub(svar1, svar2); in exec_dsp()
117 sres = qsub(svar1, svar2); in exec_dsp()
123 sres = qsub(svar1, svar2); in exec_dsp()
129 sres = qsub(svar1, svar2); in exec_dsp()
135 sres = qsub(svar1, svar2); in exec_dsp()
141 sres = qsub(svar1, svar2); in exec_dsp()
147 sres = qsub(svar1, svar2); in exec_dsp()
|
| D | ref-rvct-all.txt | 7980 qsub(0x1, 0x2) = 0xffffffff sat 0
7981 qsub(0xffffffff, 0xfffffffe) = 0x1 sat 0
7982 qsub(0xffffffff, 0x2) = 0xfffffffd sat 0
7983 qsub(0x7000, 0xffff9000) = 0xe000 sat 0
7984 qsub(0x8fff, 0xffff7001) = 0x11ffe sat 0
7985 qsub(0x70000000, 0x90000000) = 0x7fffffff sat 1
7986 qsub(0x8fffffff, 0x70000001) = 0x80000000 sat 1
7987 qsub(0, 0x80000000) = 0x7fffffff sat 1
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics-v5.ll | 74 define i32 @qsub(i32 %a, i32 %b) nounwind {
75 ; CHECK-LABEL: qsub
76 ; CHECK: qsub r0, r0, r1
77 %tmp = call i32 @llvm.arm.qsub(i32 %a, i32 %b)
93 %add = call i32 @llvm.arm.qsub(i32 %a, i32 %dbl)
110 declare i32 @llvm.arm.qsub(i32, i32) nounwind
|
| D | ssub_sat.ll | 67 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
85 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
90 ; CHECK-ARMDSP-NEXT: qsub r0, r0, r1
293 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
354 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
400 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
417 ; CHECK-ARMBASEDSP-NEXT: qsub r0, r0, r1
425 ; CHECK-ARMDSP-NEXT: qsub r0, r0, r1
598 ; CHECK-T2DSP-NEXT: qsub r0, r0, r12
600 ; CHECK-T2DSP-NEXT: qsub r1, r1, r12
[all …]
|
| D | ssub_sat_plus.ll | 70 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
76 ; CHECK-ARM-NEXT: qsub r0, r0, r1
369 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
378 ; CHECK-ARM-NEXT: qsub r0, r0, r1
|
| D | qdadd.ll | 172 ; CHECK-T2DSP-NEXT: qsub r0, r0, r1
178 ; CHECK-ARM-NEXT: qsub r0, r0, r1
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 795 qsub, // 9
1124 { 0, 64 }, // qsub
5191 … { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1",…
5204 LaneBitmask(0x00000004), // qsub
9025 &LaneMaskComposeSequences[10], // to qsub
9156 0, // qsub
9257 0, // qsub
9358 0, // qsub
9459 0, // qsub
9560 0, // qsub
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-t32.cc | 108 M(qsub)
|
| D | test-assembler-cond-rd-rn-rm-a32.cc | 109 M(qsub)
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | m7-int.s | 215 qsub r0, r1, r2 label
647 # CHECK-NEXT: 1 2 1.00 qsub r0, r1, r2
1087 …0.50 - - - - 1.00 - - - - - - qsub r0, r1, r2
|
| D | m4-int.s | 222 qsub r0, r1, r2 label
669 # CHECK-NEXT: 1 1 1.00 qsub r0, r1, r2
1107 # CHECK-NEXT: 1.00 qsub r0, r1, r2
|
| D | cortex-a57-basic-instructions.s | 428 qsub r1, r2, r3
1298 # CHECK-NEXT: 1 2 1.00 U qsub r1, r2, r3
2175 # CHECK-NEXT: - - - - 1.00 - - - qsub r1, r2, r3
|
| D | cortex-a57-thumb.s | 491 qsub r1, r2, r3
1399 # CHECK-NEXT: 1 2 1.00 qsub r1, r2, r3
2313 # CHECK-NEXT: - - - - 1.00 - - - qsub r1, r2, r3
|
| /external/llvm-project/llvm/test/CodeGen/Thumb2/ |
| D | mve-qrintr.ll | 213 …%3 = tail call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %2, <4 x i32> %.splat,…
681 declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 …
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 32 def qsub : SubRegIndex<64>;
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 502 0x52,0x10,0x23,0xe1 = qsub r1, r2, r3
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 31 def qsub : SubRegIndex<64>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 31 def qsub : SubRegIndex<64>;
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2845 void qsub(Condition cond, Register rd, Register rm, Register rn);
2846 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } in qsub() function
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1859 qsub r1, r2, r3
1866 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1829 qsub r1, r2, r3
1836 @ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1]
|