/external/llvm-project/llvm/test/MC/AMDGPU/ |
D | mimg.s | 39 image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 48 image_load v5, v[1:4], s[8:15] r128 72 image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16 82 image_store v5, v[1:4], s[8:15] r128 330 image_sample v193, v[237:240], s[28:35], s[4:7] r128 443 image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
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D | gfx9_err_pos.s | 163 image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | MIMGInstructions.td | 229 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 231 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 241 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 254 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" 322 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 324 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 334 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe), 336 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe" [all …]
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D | SIInstrFormats.td | 269 bits<1> r128; 280 let Inst{15} = r128;
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D | AMDGPU.td | 36 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128", 360 def FeatureR128A16 : SubtargetFeature<"r128-a16",
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | MIMGInstructions.td | 245 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 247 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 257 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 259 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 270 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 272 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" 338 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 340 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 350 … GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe), 352 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe" [all …]
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D | SIInstrFormats.td | 275 bits<1> r128; 286 let Inst{15} = r128;
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D | AMDGPU.td | 42 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128", 390 def FeatureR128A16 : SubtargetFeature<"r128-a16", 393 … A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128"
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/external/llvm/test/CodeGen/X86/ |
D | avx512-i1test.ll | 28 %r128 = and i64 %r111, 576460752303423488 29 %phitmp = icmp eq i64 %r128, 0
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/external/llvm-project/llvm/docs/AMDGPU/ |
D | gfx7_rsrc_mimg.rst | 15 *Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
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D | gfx10_rsrc_mimg.rst | 15 *Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
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D | gfx8_rsrc_mimg.rst | 15 *Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
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/external/llvm-project/llvm/test/CodeGen/X86/ |
D | avx512-i1test.ll | 44 %r128 = and i64 %r111, 576460752303423488 45 %phitmp = icmp eq i64 %r128, 0
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/external/ltp/runtest/ |
D | ltp-aio-stress.part1 | 39 ADS1010 aio-stress -I500 -o3 -S -r128 -t4 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file3 $TMPDIR/… 52 ADS1023 aio-stress -I500 -o3 -O -r128 -t4 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $TMPDIR… 65 ADS1036 aio-stress -I500 -o1 -S -r128 -t4 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 $T… 78 ADS1049 aio-stress -I500 -o1 -O -r128 -t8 $TMPDIR/junkfile $TMPDIR/file2 $TMPDIR/file7 …
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/external/llvm/include/llvm/IR/ |
D | IntrinsicsAMDGPU.td | 195 llvm_i1_ty, // r128(imm) 210 llvm_i1_ty, // r128(imm) 224 llvm_i1_ty, // r128(imm) 247 llvm_i1_ty, // r128(imm)
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/external/llvm/lib/Target/AMDGPU/ |
D | SIIntrinsics.td | 63 llvm_i32_ty, // r128(imm) 78 llvm_i32_ty, // r128(imm)
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D | SIInstrInfo.td | 558 def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>; 3387 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 3388 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da", 3418 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 3419 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 3451 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 3452 asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" 3511 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), 3512 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da", 3548 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), [all …]
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D | SIInstrFormats.td | 573 bits<1> r128; 585 let Inst{15} = r128;
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D | SIInstructions.td | 2526 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 2529 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2543 imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe), 2546 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) 2556 (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc, 2560 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2570 (name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da, 2574 (as_i1imm $r128), 0, 0, (as_i1imm $da)) 2584 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), 2585 (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)) [all …]
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/external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
D | unsupported-image-a16.ll | 4 ; Make sure this doesn't assert on targets without the r128-16
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/external/mesa3d/docs/relnotes/ |
D | 8.0.rst | 48 i810, mach64, mga, r128, savage, sis, tdfx, and unichrome were
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/external/fonttools/Lib/fontTools/pens/ |
D | momentsPen.py | 268 r128 = 21*r55 285 …119 - 9*r120 - r122*r53 + r123 + 54*r124 + 60*r125 + 54*r126 + r127*r35 + r128*y3 - r129*x1 + 81*r… 286 …2 + 27*r51*y2 + 15*r51*y3)/9240 - r52*(r56 + r63 + r78 + r79)/9240 - r53*(r128 + r25*y3 + 42*r43 +…
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/external/mesa3d/src/amd/compiler/ |
D | aco_opt_value_numbering.cpp | 320 aM->r128 == bM->r128 && in operator ()()
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D | aco_assembler.cpp | 441 assert(!mimg->r128); in emit_instruction() 445 …encoding |= mimg->r128 ? 1 << 15 : 0; /* GFX10: A16 moved to 2nd word, R128 replaces it in 1st wor… in emit_instruction()
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/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
D | mimg_vi.txt | 33 # FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC. 35 # VI: image_load v5, v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1…
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