| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 14 0x06,0x40,0xa5,0xe0 = adc r4, r5, r6
15 0x86,0x40,0xa5,0xe0 = adc r4, r5, r6, lsl #1
16 0x86,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsl #31
17 0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1
18 0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #31
19 0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #32
20 0xc6,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #1
21 0xc6,0x4f,0xa5,0xe0 = adc r4, r5, r6, asr #31
22 0x46,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #32
23 0xe6,0x40,0xa5,0xe0 = adc r4, r5, r6, ror #1
[all …]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc | 99 {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
106 {{gt, r6, r4, r3}, true, gt, "gt r6 r4 r3", "gt_r6_r4_r3"},
108 {{eq, r4, r6, r0}, true, eq, "eq r4 r6 r0", "eq_r4_r6_r0"},
109 {{mi, r2, r6, r1}, true, mi, "mi r2 r6 r1", "mi_r2_r6_r1"},
111 {{hi, r6, r0, r2}, true, hi, "hi r6 r0 r2", "hi_r6_r0_r2"},
117 {{eq, r6, r0, r6}, true, eq, "eq r6 r0 r6", "eq_r6_r0_r6"},
122 {{cc, r1, r6, r7}, true, cc, "cc r1 r6 r7", "cc_r1_r6_r7"},
125 {{lt, r6, r3, r3}, true, lt, "lt r6 r3 r3", "lt_r6_r3_r3"},
127 {{ge, r6, r2, r3}, true, ge, "ge r6 r2 r3", "ge_r6_r2_r3"},
128 {{cc, r5, r6, r6}, true, cc, "cc r5 r6 r6", "cc_r5_r6_r6"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc | 101 {{eq, r0, r6, r0}, true, eq, "eq r0 r6 r0", "eq_r0_r6_r0"},
109 {{eq, r1, r6, r1}, true, eq, "eq r1 r6 r1", "eq_r1_r6_r1"},
117 {{eq, r2, r6, r2}, true, eq, "eq r2 r6 r2", "eq_r2_r6_r2"},
125 {{eq, r3, r6, r3}, true, eq, "eq r3 r6 r3", "eq_r3_r6_r3"},
133 {{eq, r4, r6, r4}, true, eq, "eq r4 r6 r4", "eq_r4_r6_r4"},
141 {{eq, r5, r6, r5}, true, eq, "eq r5 r6 r5", "eq_r5_r6_r5"},
143 {{eq, r6, r0, r6}, true, eq, "eq r6 r0 r6", "eq_r6_r0_r6"},
144 {{eq, r6, r1, r6}, true, eq, "eq r6 r1 r6", "eq_r6_r1_r6"},
145 {{eq, r6, r2, r6}, true, eq, "eq r6 r2 r6", "eq_r6_r2_r6"},
146 {{eq, r6, r3, r6}, true, eq, "eq r6 r3 r6", "eq_r6_r3_r6"},
[all …]
|
| D | test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc | 106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
112 {{hi, r6, r6, r3}, true, hi, "hi r6 r6 r3", "hi_r6_r6_r3"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
120 {{pl, r0, r0, r6}, true, pl, "pl r0 r0 r6", "pl_r0_r0_r6"},
122 {{cc, r3, r3, r6}, true, cc, "cc r3 r3 r6", "cc_r3_r3_r6"},
141 {{hi, r0, r0, r6}, true, hi, "hi r0 r0 r6", "hi_r0_r0_r6"},
154 {{vs, r6, r6, r3}, true, vs, "vs r6 r6 r3", "vs_r6_r6_r3"},
166 {{ls, r6, r6, r1}, true, ls, "ls r6 r6 r1", "ls_r6_r6_r1"},
168 {{ls, r6, r6, r7}, true, ls, "ls r6 r6 r7", "ls_r6_r6_r7"},
171 {{pl, r7, r7, r6}, true, pl, "pl r7 r7 r6", "pl_r7_r7_r6"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
105 {{le, r3, r3, ASR, r6}, true, le, "le r3 r3 ASR r6", "le_r3_r3_ASR_r6"},
109 {{le, r5, r5, LSR, r6}, true, le, "le r5 r5 LSR r6", "le_r5_r5_LSR_r6"},
110 {{cs, r0, r0, ASR, r6}, true, cs, "cs r0 r0 ASR r6", "cs_r0_r0_ASR_r6"},
112 {{hi, r5, r5, LSL, r6}, true, hi, "hi r5 r5 LSL r6", "hi_r5_r5_LSL_r6"},
113 {{ls, r6, r6, LSL, r3}, true, ls, "ls r6 r6 LSL r3", "ls_r6_r6_LSL_r3"},
119 {{ls, r6, r6, LSR, r0}, true, ls, "ls r6 r6 LSR r0", "ls_r6_r6_LSR_r0"},
121 {{cc, r1, r1, LSL, r6}, true, cc, "cc r1 r1 LSL r6", "cc_r1_r1_LSL_r6"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc | 1633 {{al, r6, r6, 0}, false, al, "al r6 r6 0", "al_r6_r6_0"},
1634 {{al, r6, r6, 1}, false, al, "al r6 r6 1", "al_r6_r6_1"},
1635 {{al, r6, r6, 2}, false, al, "al r6 r6 2", "al_r6_r6_2"},
1636 {{al, r6, r6, 3}, false, al, "al r6 r6 3", "al_r6_r6_3"},
1637 {{al, r6, r6, 4}, false, al, "al r6 r6 4", "al_r6_r6_4"},
1638 {{al, r6, r6, 5}, false, al, "al r6 r6 5", "al_r6_r6_5"},
1639 {{al, r6, r6, 6}, false, al, "al r6 r6 6", "al_r6_r6_6"},
1640 {{al, r6, r6, 7}, false, al, "al r6 r6 7", "al_r6_r6_7"},
1641 {{al, r6, r6, 8}, false, al, "al r6 r6 8", "al_r6_r6_8"},
1642 {{al, r6, r6, 9}, false, al, "al r6 r6 9", "al_r6_r6_9"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc | 101 {{eq, r0, r6, 0}, true, eq, "eq r0 r6 0", "eq_r0_r6_0"},
109 {{eq, r1, r6, 0}, true, eq, "eq r1 r6 0", "eq_r1_r6_0"},
117 {{eq, r2, r6, 0}, true, eq, "eq r2 r6 0", "eq_r2_r6_0"},
125 {{eq, r3, r6, 0}, true, eq, "eq r3 r6 0", "eq_r3_r6_0"},
133 {{eq, r4, r6, 0}, true, eq, "eq r4 r6 0", "eq_r4_r6_0"},
141 {{eq, r5, r6, 0}, true, eq, "eq r5 r6 0", "eq_r5_r6_0"},
143 {{eq, r6, r0, 0}, true, eq, "eq r6 r0 0", "eq_r6_r0_0"},
144 {{eq, r6, r1, 0}, true, eq, "eq r6 r1 0", "eq_r6_r1_0"},
145 {{eq, r6, r2, 0}, true, eq, "eq r6 r2 0", "eq_r6_r2_0"},
146 {{eq, r6, r3, 0}, true, eq, "eq r6 r3 0", "eq_r6_r3_0"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc | 101 {{eq, r0, r6}, true, eq, "eq r0 r6", "eq_r0_r6"},
109 {{eq, r1, r6}, true, eq, "eq r1 r6", "eq_r1_r6"},
117 {{eq, r2, r6}, true, eq, "eq r2 r6", "eq_r2_r6"},
125 {{eq, r3, r6}, true, eq, "eq r3 r6", "eq_r3_r6"},
133 {{eq, r4, r6}, true, eq, "eq r4 r6", "eq_r4_r6"},
141 {{eq, r5, r6}, true, eq, "eq r5 r6", "eq_r5_r6"},
143 {{eq, r6, r0}, true, eq, "eq r6 r0", "eq_r6_r0"},
144 {{eq, r6, r1}, true, eq, "eq r6 r1", "eq_r6_r1"},
145 {{eq, r6, r2}, true, eq, "eq r6 r2", "eq_r6_r2"},
146 {{eq, r6, r3}, true, eq, "eq r6 r3", "eq_r6_r3"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc | 99 {{ls, r1, r6, 0}, true, ls, "ls r1 r6 0", "ls_r1_r6_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
116 {{ls, r6, r6, 4}, true, ls, "ls r6 r6 4", "ls_r6_r6_4"},
122 {{ls, r6, r3, 0}, true, ls, "ls r6 r3 0", "ls_r6_r3_0"},
125 {{eq, r6, r1, 4}, true, eq, "eq r6 r1 4", "eq_r6_r1_4"},
126 {{gt, r6, r0, 1}, true, gt, "gt r6 r0 1", "gt_r6_r0_1"},
135 {{le, r4, r6, 6}, true, le, "le r4 r6 6", "le_r4_r6_6"},
142 {{ne, r6, r3, 0}, true, ne, "ne r6 r3 0", "ne_r6_r3_0"},
149 {{hi, r2, r6, 0}, true, hi, "hi r2 r6 0", "hi_r2_r6_0"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc | 145 {{al, r0, r6, 0}, false, al, "al r0 r6 0", "al_r0_r6_0"},
146 {{al, r0, r6, 1}, false, al, "al r0 r6 1", "al_r0_r6_1"},
147 {{al, r0, r6, 2}, false, al, "al r0 r6 2", "al_r0_r6_2"},
148 {{al, r0, r6, 3}, false, al, "al r0 r6 3", "al_r0_r6_3"},
149 {{al, r0, r6, 4}, false, al, "al r0 r6 4", "al_r0_r6_4"},
150 {{al, r0, r6, 5}, false, al, "al r0 r6 5", "al_r0_r6_5"},
151 {{al, r0, r6, 6}, false, al, "al r0 r6 6", "al_r0_r6_6"},
152 {{al, r0, r6, 7}, false, al, "al r0 r6 7", "al_r0_r6_7"},
209 {{al, r1, r6, 0}, false, al, "al r1 r6 0", "al_r1_r6_0"},
210 {{al, r1, r6, 1}, false, al, "al r1 r6 1", "al_r1_r6_1"},
[all …]
|
| D | test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc | 98 {{vc, r6, r6, 138}, true, vc, "vc r6 r6 138", "vc_r6_r6_138"},
100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"},
108 {{le, r6, r6, 39}, true, le, "le r6 r6 39", "le_r6_r6_39"},
124 {{ge, r6, r6, 88}, true, ge, "ge r6 r6 88", "ge_r6_r6_88"},
137 {{cs, r6, r6, 78}, true, cs, "cs r6 r6 78", "cs_r6_r6_78"},
149 {{eq, r6, r6, 158}, true, eq, "eq r6 r6 158", "eq_r6_r6_158"},
158 {{mi, r6, r6, 99}, true, mi, "mi r6 r6 99", "mi_r6_r6_99"},
161 {{hi, r6, r6, 74}, true, hi, "hi r6 r6 74", "hi_r6_r6_74"},
172 {{lt, r6, r6, 229}, true, lt, "lt r6 r6 229", "lt_r6_r6_229"},
192 {{vs, r6, r6, 79}, true, vs, "vs r6 r6 79", "vs_r6_r6_79"},
[all …]
|
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
97 {{gt, r4, r6, LSR, 32}, true, gt, "gt r4 r6 LSR 32", "gt_r4_r6_LSR_32"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
106 {{gt, r6, r4, LSR, 13}, true, gt, "gt r6 r4 LSR 13", "gt_r6_r4_LSR_13"},
107 {{hi, r6, r5, LSR, 12}, true, hi, "hi r6 r5 LSR 12", "hi_r6_r5_LSR_12"},
108 {{pl, r6, r1, ASR, 12}, true, pl, "pl r6 r1 ASR 12", "pl_r6_r1_ASR_12"},
110 {{mi, r7, r6, ASR, 20}, true, mi, "mi r7 r6 ASR 20", "mi_r7_r6_ASR_20"},
111 {{cc, r3, r6, ASR, 22}, true, cc, "cc r3 r6 ASR 22", "cc_r3_r6_ASR_22"},
115 {{pl, r6, r4, ASR, 6}, true, pl, "pl r6 r4 ASR 6", "pl_r6_r4_ASR_6"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc | 97 {{cs, r6, r2, LSL, 8}, true, cs, "cs r6 r2 LSL 8", "cs_r6_r2_LSL_8"},
101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"},
106 {{vs, r6, r0, LSL, 26}, true, vs, "vs r6 r0 LSL 26", "vs_r6_r0_LSL_26"},
116 {{gt, r6, r4, LSL, 23}, true, gt, "gt r6 r4 LSL 23", "gt_r6_r4_LSL_23"},
121 {{le, r6, r6, LSL, 11}, true, le, "le r6 r6 LSL 11", "le_r6_r6_LSL_11"},
124 {{eq, r3, r6, LSL, 12}, true, eq, "eq r3 r6 LSL 12", "eq_r3_r6_LSL_12"},
129 {{vc, r6, r0, LSL, 13}, true, vc, "vc r6 r0 LSL 13", "vc_r6_r0_LSL_13"},
134 {{vc, r5, r6, LSL, 5}, true, vc, "vc r5 r6 LSL 5", "vc_r5_r6_LSL_5"},
135 {{cc, r6, r1, LSL, 14}, true, cc, "cc r6 r1 LSL 14", "cc_r6_r1_LSL_14"},
139 {{eq, r6, r2, LSL, 19}, true, eq, "eq r6 r2 LSL 19", "eq_r6_r2_LSL_19"},
[all …]
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| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | cortex-a57-basic-instructions.s | 21 adc r4, r5, r6
22 adc pc, r5, r6
23 adc r4, r5, r6, lsl #1
24 adc pc, r5, r6, lsl #4
25 adc r4, r5, r6, lsl #31
26 adc r4, r5, r6, lsr #1
27 adc r4, r5, r6, lsr #31
28 adc r4, r5, r6, lsr #32
29 adc r4, r5, r6, asr #1
30 adc r4, r5, r6, asr #31
[all …]
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_apply_scale_fac.s | 48 LDR r6, [sp, #0x30]
69 SUBS r6, r11, r5, ASR #2
79 SUB r14, r6, #1
82 LDRD r6, [r0, #0]
84 SMULWB r6, r6, r5
87 MOV r6, r6, ASR r14
90 STRD r6, [r0], #8
92 LDRD r6, [r0, #0]
94 SMULWB r6, r6, r5
98 MOV r6, r6, ASR r14
[all …]
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| /external/libmpeg2/common/arm/ |
| D | impeg2_format_conv.s | 139 mov r6, r5
145 sub r6, r6, #16
146 cmp r6, #15
149 cmp r6, #0
155 rsb r6, r6, #16
156 sub r0, r0, r6
157 sub r3, r3, r6
191 mov r6, r5
200 sub r6, r6, #8
201 cmp r6, #7
[all …]
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| /external/llvm-project/compiler-rt/lib/builtins/arm/ |
| D | addsf3.S | 27 push {r4, r5, r6, r7, lr}
37 lsrs r6, r2, #(significandBits)
39 cmp r6, #0xFF
62 movs r6, #1
63 lsls r6, r6, #(significandBits + 3)
68 orrs r4, r6
74 orrs r5, r6
78 subs r6, r2, r3
85 subs r6, r6, #1
91 subs r3, r3, r6
[all …]
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| /external/skqp/src/compute/hs/cuda/sm_35/u64/ |
| D | hs_cuda_u64.cu | 35 HS_KEY_TYPE r6 = HS_SLAB_GLOBAL_LOAD(vin, 5); variable
39 HS_CMP_XCHG(r2, r6);
45 HS_CMP_XCHG(r6, r8);
47 HS_CMP_XCHG(r4, r6);
50 HS_CMP_XCHG(r5, r6);
56 HS_CMP_XCHG(r6, r7);
61 HS_CMP_FLIP(2, r3, r6);
68 HS_CMP_XCHG(r2, r6);
71 HS_CMP_XCHG(r6, r8);
74 HS_CMP_XCHG(r5, r6);
[all …]
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| /external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 45 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
47 ldmia r0,{r3,r4,r5,r6,r7}
53 mov r6,r6,ror#30
63 eor r10,r5,r6 @ F_xx_xx
70 eor r10,r5,r6 @ F_xx_xx
78 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
85 add r6,r8,r6,ror#2 @ E+=K_00_19
90 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
94 add r6,r8,r6,ror#2 @ E+=K_00_19
96 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 45 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
47 ldmia r0,{r3,r4,r5,r6,r7}
53 mov r6,r6,ror#30
63 eor r10,r5,r6 @ F_xx_xx
70 eor r10,r5,r6 @ F_xx_xx
78 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
85 add r6,r8,r6,ror#2 @ E+=K_00_19
90 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
94 add r6,r8,r6,ror#2 @ E+=K_00_19
96 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
|
| /external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 46 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
48 ldmia r0,{r3,r4,r5,r6,r7}
54 mov r6,r6,ror#30
64 eor r10,r5,r6 @ F_xx_xx
71 eor r10,r5,r6 @ F_xx_xx
79 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
86 add r6,r8,r6,ror#2 @ E+=K_00_19
91 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
95 add r6,r8,r6,ror#2 @ E+=K_00_19
97 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 46 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
48 ldmia r0,{r3,r4,r5,r6,r7}
54 mov r6,r6,ror#30
64 eor r10,r5,r6 @ F_xx_xx
71 eor r10,r5,r6 @ F_xx_xx
79 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
86 add r6,r8,r6,ror#2 @ E+=K_00_19
91 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
95 add r6,r8,r6,ror#2 @ E+=K_00_19
97 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 45 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
47 ldmia r0,{r3,r4,r5,r6,r7}
53 mov r6,r6,ror#30
63 eor r10,r5,r6 @ F_xx_xx
70 eor r10,r5,r6 @ F_xx_xx
78 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
85 add r6,r8,r6,ror#2 @ E+=K_00_19
90 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
94 add r6,r8,r6,ror#2 @ E+=K_00_19
96 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha1-armv4-large.S | 46 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
48 ldmia r0,{r3,r4,r5,r6,r7}
54 mov r6,r6,ror#30
64 eor r10,r5,r6 @ F_xx_xx
71 eor r10,r5,r6 @ F_xx_xx
79 eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
86 add r6,r8,r6,ror#2 @ E+=K_00_19
91 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
95 add r6,r8,r6,ror#2 @ E+=K_00_19
97 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
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| /external/skqp/src/compute/hs/cl/intel/gen8/u32/ |
| D | hs_kernels.cl | 26 HS_KEY_TYPE r6 = HS_SLAB_GLOBAL_LOAD(vin, 5);
30 HS_CMP_XCHG(r2, r6);
36 HS_CMP_XCHG(r6, r8);
38 HS_CMP_XCHG(r4, r6);
41 HS_CMP_XCHG(r5, r6);
47 HS_CMP_XCHG(r6, r7);
52 HS_CMP_FLIP(2, r3, r6);
59 HS_CMP_XCHG(r2, r6);
62 HS_CMP_XCHG(r6, r8);
65 HS_CMP_XCHG(r5, r6);
[all …]
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