Searched refs:ra_alloc_reg_set (Results 1 – 10 of 10) sorted by relevance
| /external/mesa3d/src/util/ |
| D | register_allocate.h | 53 struct ra_regs *ra_alloc_reg_set(void *mem_ctx, unsigned int count,
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| D | register_allocate.c | 213 ra_alloc_reg_set(void *mem_ctx, unsigned int count, bool need_conflict_lists) in ra_alloc_reg_set() function
455 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, reg_count, false); in ra_set_deserialize()
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_ra.c | 87 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, ETNA_MAX_TEMPS * in etna_ra_setup()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_ra_regset.c | 125 set->regs = ra_alloc_reg_set(set, ra_reg_count, true); in ir3_ra_alloc_reg_set()
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_register_allocate.c | 118 vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true); in vc4_alloc_reg_set()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_reg_allocate.cpp | 116 compiler->vec4_reg_set.regs = ra_alloc_reg_set(compiler, ra_reg_count, false); in brw_vec4_alloc_reg_set()
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| D | brw_fs_reg_allocate.cpp | 154 struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count, false); in brw_alloc_reg_set()
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| /external/mesa3d/src/broadcom/compiler/ |
| D | vir_register_allocate.c | 411 compiler->regs = ra_alloc_reg_set(compiler, PHYS_INDEX + PHYS_COUNT, in vir_init_reg_sets()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_pair_regalloc.c | 696 s->regs = ra_alloc_reg_set(NULL, R500_PFS_NUM_TEMP_REGS * RC_MASK_XYZW, in rc_init_regalloc_state()
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| /external/mesa3d/src/gallium/drivers/lima/ir/pp/ |
| D | regalloc.c | 97 struct ra_regs *ret = ra_alloc_reg_set(mem_ctx, PPIR_REG_COUNT, false); in ppir_regalloc_init()
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