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Searched refs:radeon_enc_code_fixed_bits (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_enc_2_0.c113 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps_hevc()
114 radeon_enc_code_fixed_bits(enc, 0x4201, 16); in radeon_enc_nalu_sps_hevc()
117 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_sps_hevc()
118 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
119 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
120 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
121 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_sps_hevc()
122 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_sps_hevc()
125 radeon_enc_code_fixed_bits(enc, 0x20000000, 32); in radeon_enc_nalu_sps_hevc()
127 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_sps_hevc()
[all …]
Dradeon_vcn_enc_1_2.c288 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps()
289 radeon_enc_code_fixed_bits(enc, 0x67, 8); in radeon_enc_nalu_sps()
292 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8); in radeon_enc_nalu_sps()
293 radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline in radeon_enc_nalu_sps()
294 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8); in radeon_enc_nalu_sps()
305 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps()
315 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, in radeon_enc_nalu_sps()
320 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1); in radeon_enc_nalu_sps()
323 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
325 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
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Dradeon_vcn_enc_3_0.c121 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps_hevc()
122 radeon_enc_code_fixed_bits(enc, 0x4401, 16); in radeon_enc_nalu_pps_hevc()
127 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
128 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_pps_hevc()
129 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
130 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
134 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1); in radeon_enc_nalu_pps_hevc()
135 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
138 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
140 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
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Dradeon_vcn_enc.c519 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, in radeon_enc_code_fixed_bits() function
562 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros); in radeon_enc_byte_align()
595 radeon_enc_code_fixed_bits(enc, ue_code, ue_length); in radeon_enc_code_ue()
Dradeon_vcn_enc.h554 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,