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Searched refs:radeon_set_config_reg (Results 1 – 15 of 15) sorted by relevance

/external/mesa3d/src/gallium/drivers/r600/
Dr600_state.c1294 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); in r600_emit_msaa_state()
1298 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); in r600_emit_msaa_state()
1657 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); in r600_emit_config_state()
1658 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2); in r600_emit_config_state()
1894 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); in r600_emit_seamless_cube_map()
1963 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_emit_gs_rings()
1969 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); in r600_emit_gs_rings()
1974 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, in r600_emit_gs_rings()
1978 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); in r600_emit_gs_rings()
1983 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, in r600_emit_gs_rings()
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Dr600_cs.h139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
Dr600_hw_context.c138 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until); in r600_flush_emit()
569 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, in r600_cp_dma_copy_buffer()
Dr600_state_common.c1687 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_setup_scratch_area_for_shader()
1698 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX, in r600_setup_scratch_area_for_shader()
1705 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8); in r600_setup_scratch_area_for_shader()
1711 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8); in r600_setup_scratch_area_for_shader()
1716 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX, in r600_setup_scratch_area_for_shader()
1723 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_setup_scratch_area_for_shader()
2285 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, in r600_draw_vbo()
2404 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_draw_vbo()
Devergreen_compute.c633 radeon_set_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size); in evergreen_emit_dispatch()
640 radeon_set_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE, in evergreen_emit_dispatch()
805 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8)); in compute_emit_cs()
Dr600_streamout.c167 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in r600_flush_vgt_streamout()
Devergreen_state.c991 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8)); in evergreen_emit_config_state()
2673 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in evergreen_emit_gs_rings()
2679 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, in evergreen_emit_gs_rings()
2685 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, in evergreen_emit_gs_rings()
2689 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, in evergreen_emit_gs_rings()
2695 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, in evergreen_emit_gs_rings()
2698 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); in evergreen_emit_gs_rings()
2699 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); in evergreen_emit_gs_rings()
2702 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in evergreen_emit_gs_rings()
/external/mesa3d/src/amd/vulkan/
Dradv_cs.h52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
Dsi_cmd_buffer.c54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
141 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_compute()
223 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | in si_emit_graphics()
Dradv_device.c3417 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE, in radv_emit_tess_factor_ring()
3419 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE, in radv_emit_tess_factor_ring()
3421 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM, in radv_emit_tess_factor_ring()
Dradv_cmd_buffer.c1486 radeon_set_config_reg(cmd_buffer->cs, in radv_emit_primitive_topology()
6681 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in radv_flush_vgt_streamout()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
Dsi_state_streamout.c284 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in si_flush_vgt_streamout()
Dsi_compute.c369 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_initial_compute_regs()
Dsi_state_draw.c741 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim); in si_emit_draw_registers()