/external/mesa3d/src/gallium/drivers/r600/ |
D | r600_state.c | 1294 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); in r600_emit_msaa_state() 1298 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); in r600_emit_msaa_state() 1657 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); in r600_emit_config_state() 1658 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2); in r600_emit_config_state() 1894 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); in r600_emit_seamless_cube_map() 1963 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_emit_gs_rings() 1969 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); in r600_emit_gs_rings() 1974 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, in r600_emit_gs_rings() 1978 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); in r600_emit_gs_rings() 1983 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, in r600_emit_gs_rings() [all …]
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D | r600_cs.h | 139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
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D | r600_hw_context.c | 138 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until); in r600_flush_emit() 569 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, in r600_cp_dma_copy_buffer()
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D | r600_state_common.c | 1687 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_setup_scratch_area_for_shader() 1698 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX, in r600_setup_scratch_area_for_shader() 1705 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8); in r600_setup_scratch_area_for_shader() 1711 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8); in r600_setup_scratch_area_for_shader() 1716 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX, in r600_setup_scratch_area_for_shader() 1723 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_setup_scratch_area_for_shader() 2285 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, in r600_draw_vbo() 2404 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_draw_vbo()
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D | evergreen_compute.c | 633 radeon_set_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size); in evergreen_emit_dispatch() 640 radeon_set_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE, in evergreen_emit_dispatch() 805 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8)); in compute_emit_cs()
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D | r600_streamout.c | 167 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in r600_flush_vgt_streamout()
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D | evergreen_state.c | 991 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8)); in evergreen_emit_config_state() 2673 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in evergreen_emit_gs_rings() 2679 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, in evergreen_emit_gs_rings() 2685 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, in evergreen_emit_gs_rings() 2689 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, in evergreen_emit_gs_rings() 2695 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, in evergreen_emit_gs_rings() 2698 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); in evergreen_emit_gs_rings() 2699 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); in evergreen_emit_gs_rings() 2702 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in evergreen_emit_gs_rings()
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/external/mesa3d/src/amd/vulkan/ |
D | radv_cs.h | 52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
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D | si_cmd_buffer.c | 54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs() 67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs() 141 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_compute() 223 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | in si_emit_graphics()
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D | radv_device.c | 3417 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE, in radv_emit_tess_factor_ring() 3419 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE, in radv_emit_tess_factor_ring() 3421 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM, in radv_emit_tess_factor_ring()
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D | radv_cmd_buffer.c | 1486 radeon_set_config_reg(cmd_buffer->cs, in radv_emit_primitive_topology() 6681 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in radv_flush_vgt_streamout()
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_build_pm4.h | 51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
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D | si_state_streamout.c | 284 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in si_flush_vgt_streamout()
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D | si_compute.c | 369 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_initial_compute_regs()
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D | si_state_draw.c | 741 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim); in si_emit_draw_registers()
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