1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static VkResult
35 build_pipeline(struct radv_device *device,
36 VkImageAspectFlagBits aspect,
37 enum glsl_sampler_dim tex_dim,
38 unsigned fs_key,
39 VkPipeline *pipeline);
40
41 static nir_shader *
build_nir_vertex_shader(void)42 build_nir_vertex_shader(void)
43 {
44 const struct glsl_type *vec4 = glsl_vec4_type();
45 nir_builder b;
46
47 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
48 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
49
50 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
51 vec4, "gl_Position");
52 pos_out->data.location = VARYING_SLOT_POS;
53
54 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
55 vec4, "v_tex_pos");
56 tex_pos_out->data.location = VARYING_SLOT_VAR0;
57 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
58
59 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
60
61 nir_store_var(&b, pos_out, outvec, 0xf);
62
63 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
64 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
65 nir_intrinsic_set_base(src_box, 0);
66 nir_intrinsic_set_range(src_box, 16);
67 src_box->num_components = 4;
68 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
69 nir_builder_instr_insert(&b, &src_box->instr);
70
71 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
72 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
73 nir_intrinsic_set_base(src0_z, 16);
74 nir_intrinsic_set_range(src0_z, 4);
75 src0_z->num_components = 1;
76 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
77 nir_builder_instr_insert(&b, &src0_z->instr);
78
79 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
80 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
81 nir_builder_instr_insert(&b, &vertex_id->instr);
82
83 /* vertex 0 - src0_x, src0_y, src0_z */
84 /* vertex 1 - src0_x, src1_y, src0_z*/
85 /* vertex 2 - src1_x, src0_y, src0_z */
86 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
87 channel 1 is vertex id != 1 ? src_y : src_y + w */
88
89 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
90 nir_imm_int(&b, 2));
91 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
92 nir_imm_int(&b, 1));
93
94 nir_ssa_def *comp[4];
95 comp[0] = nir_bcsel(&b, c0cmp,
96 nir_channel(&b, &src_box->dest.ssa, 0),
97 nir_channel(&b, &src_box->dest.ssa, 2));
98
99 comp[1] = nir_bcsel(&b, c1cmp,
100 nir_channel(&b, &src_box->dest.ssa, 1),
101 nir_channel(&b, &src_box->dest.ssa, 3));
102 comp[2] = &src0_z->dest.ssa;
103 comp[3] = nir_imm_float(&b, 1.0);
104 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
105 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
106 return b.shader;
107 }
108
109 static nir_shader *
build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)110 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
111 {
112 char shader_name[64];
113 const struct glsl_type *vec4 = glsl_vec4_type();
114 nir_builder b;
115
116 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
117
118 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
119 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
120
121 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
122 vec4, "v_tex_pos");
123 tex_pos_in->data.location = VARYING_SLOT_VAR0;
124
125 /* Swizzle the array index which comes in as Z coordinate into the right
126 * position.
127 */
128 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
129 nir_ssa_def *const tex_pos =
130 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
131 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3));
132
133 const struct glsl_type *sampler_type =
134 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
135 glsl_get_base_type(vec4));
136 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
137 sampler_type, "s_tex");
138 sampler->data.descriptor_set = 0;
139 sampler->data.binding = 0;
140
141 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
142
143 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
144 tex->sampler_dim = tex_dim;
145 tex->op = nir_texop_tex;
146 tex->src[0].src_type = nir_tex_src_coord;
147 tex->src[0].src = nir_src_for_ssa(tex_pos);
148 tex->src[1].src_type = nir_tex_src_texture_deref;
149 tex->src[1].src = nir_src_for_ssa(tex_deref);
150 tex->src[2].src_type = nir_tex_src_sampler_deref;
151 tex->src[2].src = nir_src_for_ssa(tex_deref);
152 tex->dest_type = nir_type_float; /* TODO */
153 tex->is_array = glsl_sampler_type_is_array(sampler_type);
154 tex->coord_components = tex_pos->num_components;
155
156 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
157 nir_builder_instr_insert(&b, &tex->instr);
158
159 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
160 vec4, "f_color");
161 color_out->data.location = FRAG_RESULT_DATA0;
162 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
163
164 return b.shader;
165 }
166
167 static nir_shader *
build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)168 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
169 {
170 char shader_name[64];
171 const struct glsl_type *vec4 = glsl_vec4_type();
172 nir_builder b;
173
174 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
175
176 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
177 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
178
179 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
180 vec4, "v_tex_pos");
181 tex_pos_in->data.location = VARYING_SLOT_VAR0;
182
183 /* Swizzle the array index which comes in as Z coordinate into the right
184 * position.
185 */
186 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
187 nir_ssa_def *const tex_pos =
188 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
189 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3));
190
191 const struct glsl_type *sampler_type =
192 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
193 glsl_get_base_type(vec4));
194 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
195 sampler_type, "s_tex");
196 sampler->data.descriptor_set = 0;
197 sampler->data.binding = 0;
198
199 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
200
201 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
202 tex->sampler_dim = tex_dim;
203 tex->op = nir_texop_tex;
204 tex->src[0].src_type = nir_tex_src_coord;
205 tex->src[0].src = nir_src_for_ssa(tex_pos);
206 tex->src[1].src_type = nir_tex_src_texture_deref;
207 tex->src[1].src = nir_src_for_ssa(tex_deref);
208 tex->src[2].src_type = nir_tex_src_sampler_deref;
209 tex->src[2].src = nir_src_for_ssa(tex_deref);
210 tex->dest_type = nir_type_float; /* TODO */
211 tex->is_array = glsl_sampler_type_is_array(sampler_type);
212 tex->coord_components = tex_pos->num_components;
213
214 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
215 nir_builder_instr_insert(&b, &tex->instr);
216
217 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
218 vec4, "f_color");
219 color_out->data.location = FRAG_RESULT_DEPTH;
220 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
221
222 return b.shader;
223 }
224
225 static nir_shader *
build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)226 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
227 {
228 char shader_name[64];
229 const struct glsl_type *vec4 = glsl_vec4_type();
230 nir_builder b;
231
232 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
233
234 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
235 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
236
237 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
238 vec4, "v_tex_pos");
239 tex_pos_in->data.location = VARYING_SLOT_VAR0;
240
241 /* Swizzle the array index which comes in as Z coordinate into the right
242 * position.
243 */
244 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
245 nir_ssa_def *const tex_pos =
246 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
247 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3));
248
249 const struct glsl_type *sampler_type =
250 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
251 glsl_get_base_type(vec4));
252 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
253 sampler_type, "s_tex");
254 sampler->data.descriptor_set = 0;
255 sampler->data.binding = 0;
256
257 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
258
259 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
260 tex->sampler_dim = tex_dim;
261 tex->op = nir_texop_tex;
262 tex->src[0].src_type = nir_tex_src_coord;
263 tex->src[0].src = nir_src_for_ssa(tex_pos);
264 tex->src[1].src_type = nir_tex_src_texture_deref;
265 tex->src[1].src = nir_src_for_ssa(tex_deref);
266 tex->src[2].src_type = nir_tex_src_sampler_deref;
267 tex->src[2].src = nir_src_for_ssa(tex_deref);
268 tex->dest_type = nir_type_float; /* TODO */
269 tex->is_array = glsl_sampler_type_is_array(sampler_type);
270 tex->coord_components = tex_pos->num_components;
271
272 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
273 nir_builder_instr_insert(&b, &tex->instr);
274
275 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
276 vec4, "f_color");
277 color_out->data.location = FRAG_RESULT_STENCIL;
278 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
279
280 return b.shader;
281 }
282
283 static enum glsl_sampler_dim
translate_sampler_dim(VkImageType type)284 translate_sampler_dim(VkImageType type) {
285 switch(type) {
286 case VK_IMAGE_TYPE_1D:
287 return GLSL_SAMPLER_DIM_1D;
288 case VK_IMAGE_TYPE_2D:
289 return GLSL_SAMPLER_DIM_2D;
290 case VK_IMAGE_TYPE_3D:
291 return GLSL_SAMPLER_DIM_3D;
292 default:
293 unreachable("Unhandled image type");
294 }
295 }
296
297 static void
meta_emit_blit(struct radv_cmd_buffer * cmd_buffer,struct radv_image * src_image,struct radv_image_view * src_iview,VkImageLayout src_image_layout,float src_offset_0[3],float src_offset_1[3],struct radv_image * dest_image,struct radv_image_view * dest_iview,VkImageLayout dest_image_layout,VkOffset2D dest_offset_0,VkOffset2D dest_offset_1,VkRect2D dest_box,VkSampler sampler)298 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
299 struct radv_image *src_image,
300 struct radv_image_view *src_iview,
301 VkImageLayout src_image_layout,
302 float src_offset_0[3],
303 float src_offset_1[3],
304 struct radv_image *dest_image,
305 struct radv_image_view *dest_iview,
306 VkImageLayout dest_image_layout,
307 VkOffset2D dest_offset_0,
308 VkOffset2D dest_offset_1,
309 VkRect2D dest_box,
310 VkSampler sampler)
311 {
312 struct radv_device *device = cmd_buffer->device;
313 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
314 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
315 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
316 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
317 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
318
319 assert(src_image->info.samples == dest_image->info.samples);
320
321 float vertex_push_constants[5] = {
322 src_offset_0[0] / (float)src_width,
323 src_offset_0[1] / (float)src_height,
324 src_offset_1[0] / (float)src_width,
325 src_offset_1[1] / (float)src_height,
326 src_offset_0[2] / (float)src_depth,
327 };
328
329 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
330 device->meta_state.blit.pipeline_layout,
331 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
332 vertex_push_constants);
333
334 VkFramebuffer fb;
335 radv_CreateFramebuffer(radv_device_to_handle(device),
336 &(VkFramebufferCreateInfo) {
337 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
338 .attachmentCount = 1,
339 .pAttachments = (VkImageView[]) {
340 radv_image_view_to_handle(dest_iview),
341 },
342 .width = dst_width,
343 .height = dst_height,
344 .layers = 1,
345 }, &cmd_buffer->pool->alloc, &fb);
346 VkPipeline* pipeline = NULL;
347 unsigned fs_key = 0;
348 switch (src_iview->aspect_mask) {
349 case VK_IMAGE_ASPECT_COLOR_BIT: {
350 unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
351 fs_key = radv_format_meta_fs_key(dest_image->vk_format);
352
353 radv_cmd_buffer_begin_render_pass(cmd_buffer,
354 &(VkRenderPassBeginInfo) {
355 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
356 .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
357 .framebuffer = fb,
358 .renderArea = {
359 .offset = { dest_box.offset.x, dest_box.offset.y },
360 .extent = { dest_box.extent.width, dest_box.extent.height },
361 },
362 .clearValueCount = 0,
363 .pClearValues = NULL,
364 });
365 switch (src_image->type) {
366 case VK_IMAGE_TYPE_1D:
367 pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
368 break;
369 case VK_IMAGE_TYPE_2D:
370 pipeline = &device->meta_state.blit.pipeline_2d_src[fs_key];
371 break;
372 case VK_IMAGE_TYPE_3D:
373 pipeline = &device->meta_state.blit.pipeline_3d_src[fs_key];
374 break;
375 default:
376 unreachable("bad VkImageType");
377 }
378 break;
379 }
380 case VK_IMAGE_ASPECT_DEPTH_BIT: {
381 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
382 radv_cmd_buffer_begin_render_pass(cmd_buffer,
383 &(VkRenderPassBeginInfo) {
384 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
385 .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
386 .framebuffer = fb,
387 .renderArea = {
388 .offset = { dest_box.offset.x, dest_box.offset.y },
389 .extent = { dest_box.extent.width, dest_box.extent.height },
390 },
391 .clearValueCount = 0,
392 .pClearValues = NULL,
393 });
394 switch (src_image->type) {
395 case VK_IMAGE_TYPE_1D:
396 pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
397 break;
398 case VK_IMAGE_TYPE_2D:
399 pipeline = &device->meta_state.blit.depth_only_2d_pipeline;
400 break;
401 case VK_IMAGE_TYPE_3D:
402 pipeline = &device->meta_state.blit.depth_only_3d_pipeline;
403 break;
404 default:
405 unreachable("bad VkImageType");
406 }
407 break;
408 }
409 case VK_IMAGE_ASPECT_STENCIL_BIT: {
410 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
411 radv_cmd_buffer_begin_render_pass(cmd_buffer,
412 &(VkRenderPassBeginInfo) {
413 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
414 .renderPass = device->meta_state.blit.stencil_only_rp[ds_layout],
415 .framebuffer = fb,
416 .renderArea = {
417 .offset = { dest_box.offset.x, dest_box.offset.y },
418 .extent = { dest_box.extent.width, dest_box.extent.height },
419 },
420 .clearValueCount = 0,
421 .pClearValues = NULL,
422 });
423 switch (src_image->type) {
424 case VK_IMAGE_TYPE_1D:
425 pipeline = &device->meta_state.blit.stencil_only_1d_pipeline;
426 break;
427 case VK_IMAGE_TYPE_2D:
428 pipeline = &device->meta_state.blit.stencil_only_2d_pipeline;
429 break;
430 case VK_IMAGE_TYPE_3D:
431 pipeline = &device->meta_state.blit.stencil_only_3d_pipeline;
432 break;
433 default:
434 unreachable("bad VkImageType");
435 }
436 break;
437 }
438 default:
439 unreachable("bad VkImageType");
440 }
441
442 radv_cmd_buffer_set_subpass(cmd_buffer,
443 &cmd_buffer->state.pass->subpasses[0]);
444
445 if (!*pipeline) {
446 VkResult ret = build_pipeline(device, src_iview->aspect_mask, translate_sampler_dim(src_image->type), fs_key, pipeline);
447 if (ret != VK_SUCCESS) {
448 cmd_buffer->record_result = ret;
449 goto fail_pipeline;
450 }
451 }
452
453 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
454 VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
455
456 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
457 device->meta_state.blit.pipeline_layout,
458 0, /* set */
459 1, /* descriptorWriteCount */
460 (VkWriteDescriptorSet[]) {
461 {
462 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
463 .dstBinding = 0,
464 .dstArrayElement = 0,
465 .descriptorCount = 1,
466 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
467 .pImageInfo = (VkDescriptorImageInfo[]) {
468 {
469 .sampler = sampler,
470 .imageView = radv_image_view_to_handle(src_iview),
471 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
472 },
473 }
474 }
475 });
476
477 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
478 .x = dest_offset_0.x,
479 .y = dest_offset_0.y,
480 .width = dest_offset_1.x - dest_offset_0.x,
481 .height = dest_offset_1.y - dest_offset_0.y,
482 .minDepth = 0.0f,
483 .maxDepth = 1.0f
484 });
485
486 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
487 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
488 .extent = (VkExtent2D) {
489 abs(dest_offset_1.x - dest_offset_0.x),
490 abs(dest_offset_1.y - dest_offset_0.y)
491 },
492 });
493
494 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
495
496 fail_pipeline:
497 radv_cmd_buffer_end_render_pass(cmd_buffer);
498
499 /* At the point where we emit the draw call, all data from the
500 * descriptor sets, etc. has been used. We are free to delete it.
501 */
502 /* TODO: above comment is not valid for at least descriptor sets/pools,
503 * as we may not free them till after execution finishes. Check others. */
504
505 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
506 &cmd_buffer->pool->alloc);
507 }
508
509 static bool
flip_coords(unsigned * src0,unsigned * src1,unsigned * dst0,unsigned * dst1)510 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
511 {
512 bool flip = false;
513 if (*src0 > *src1) {
514 unsigned tmp = *src0;
515 *src0 = *src1;
516 *src1 = tmp;
517 flip = !flip;
518 }
519
520 if (*dst0 > *dst1) {
521 unsigned tmp = *dst0;
522 *dst0 = *dst1;
523 *dst1 = tmp;
524 flip = !flip;
525 }
526 return flip;
527 }
528
529 static void
blit_image(struct radv_cmd_buffer * cmd_buffer,struct radv_image * src_image,VkImageLayout src_image_layout,struct radv_image * dst_image,VkImageLayout dst_image_layout,const VkImageBlit2KHR * region,VkFilter filter)530 blit_image(struct radv_cmd_buffer *cmd_buffer,
531 struct radv_image *src_image,
532 VkImageLayout src_image_layout,
533 struct radv_image *dst_image,
534 VkImageLayout dst_image_layout,
535 const VkImageBlit2KHR *region,
536 VkFilter filter)
537 {
538 const VkImageSubresourceLayers *src_res = ®ion->srcSubresource;
539 const VkImageSubresourceLayers *dst_res = ®ion->dstSubresource;
540 struct radv_device *device = cmd_buffer->device;
541 struct radv_meta_saved_state saved_state;
542 bool old_predicating;
543 VkSampler sampler;
544
545 /* From the Vulkan 1.0 spec:
546 *
547 * vkCmdBlitImage must not be used for multisampled source or
548 * destination images. Use vkCmdResolveImage for this purpose.
549 */
550 assert(src_image->info.samples == 1);
551 assert(dst_image->info.samples == 1);
552
553 radv_CreateSampler(radv_device_to_handle(device),
554 &(VkSamplerCreateInfo) {
555 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
556 .magFilter = filter,
557 .minFilter = filter,
558 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
559 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
560 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
561 }, &cmd_buffer->pool->alloc, &sampler);
562
563 radv_meta_save(&saved_state, cmd_buffer,
564 RADV_META_SAVE_GRAPHICS_PIPELINE |
565 RADV_META_SAVE_CONSTANTS |
566 RADV_META_SAVE_DESCRIPTORS);
567
568 /* VK_EXT_conditional_rendering says that blit commands should not be
569 * affected by conditional rendering.
570 */
571 old_predicating = cmd_buffer->state.predicating;
572 cmd_buffer->state.predicating = false;
573
574 unsigned dst_start, dst_end;
575 if (dst_image->type == VK_IMAGE_TYPE_3D) {
576 assert(dst_res->baseArrayLayer == 0);
577 dst_start = region->dstOffsets[0].z;
578 dst_end = region->dstOffsets[1].z;
579 } else {
580 dst_start = dst_res->baseArrayLayer;
581 dst_end = dst_start + dst_res->layerCount;
582 }
583
584 unsigned src_start, src_end;
585 if (src_image->type == VK_IMAGE_TYPE_3D) {
586 assert(src_res->baseArrayLayer == 0);
587 src_start = region->srcOffsets[0].z;
588 src_end = region->srcOffsets[1].z;
589 } else {
590 src_start = src_res->baseArrayLayer;
591 src_end = src_start + src_res->layerCount;
592 }
593
594 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
595 float src_z_step = (float)(src_end - src_start) /
596 (float)(dst_end - dst_start);
597
598 /* There is no interpolation to the pixel center during
599 * rendering, so add the 0.5 offset ourselves here. */
600 float depth_center_offset = 0;
601 if (src_image->type == VK_IMAGE_TYPE_3D)
602 depth_center_offset = 0.5 / (dst_end - dst_start) * (src_end - src_start);
603
604 if (flip_z) {
605 src_start = src_end;
606 src_z_step *= -1;
607 depth_center_offset *= -1;
608 }
609
610 unsigned src_x0 = region->srcOffsets[0].x;
611 unsigned src_x1 = region->srcOffsets[1].x;
612 unsigned dst_x0 = region->dstOffsets[0].x;
613 unsigned dst_x1 = region->dstOffsets[1].x;
614
615 unsigned src_y0 = region->srcOffsets[0].y;
616 unsigned src_y1 = region->srcOffsets[1].y;
617 unsigned dst_y0 = region->dstOffsets[0].y;
618 unsigned dst_y1 = region->dstOffsets[1].y;
619
620 VkRect2D dst_box;
621 dst_box.offset.x = MIN2(dst_x0, dst_x1);
622 dst_box.offset.y = MIN2(dst_y0, dst_y1);
623 dst_box.extent.width = dst_x1 - dst_x0;
624 dst_box.extent.height = dst_y1 - dst_y0;
625
626 const unsigned num_layers = dst_end - dst_start;
627 for (unsigned i = 0; i < num_layers; i++) {
628 struct radv_image_view dst_iview, src_iview;
629
630 const VkOffset2D dst_offset_0 = {
631 .x = dst_x0,
632 .y = dst_y0,
633 };
634 const VkOffset2D dst_offset_1 = {
635 .x = dst_x1,
636 .y = dst_y1,
637 };
638
639 float src_offset_0[3] = {
640 src_x0,
641 src_y0,
642 src_start + i * src_z_step + depth_center_offset,
643 };
644 float src_offset_1[3] = {
645 src_x1,
646 src_y1,
647 src_start + i * src_z_step + depth_center_offset,
648 };
649 const uint32_t dst_array_slice = dst_start + i;
650
651 /* 3D images have just 1 layer */
652 const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
653
654 radv_image_view_init(&dst_iview, cmd_buffer->device,
655 &(VkImageViewCreateInfo) {
656 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
657 .image = radv_image_to_handle(dst_image),
658 .viewType = radv_meta_get_view_type(dst_image),
659 .format = dst_image->vk_format,
660 .subresourceRange = {
661 .aspectMask = dst_res->aspectMask,
662 .baseMipLevel = dst_res->mipLevel,
663 .levelCount = 1,
664 .baseArrayLayer = dst_array_slice,
665 .layerCount = 1
666 },
667 }, NULL);
668 radv_image_view_init(&src_iview, cmd_buffer->device,
669 &(VkImageViewCreateInfo) {
670 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
671 .image = radv_image_to_handle(src_image),
672 .viewType = radv_meta_get_view_type(src_image),
673 .format = src_image->vk_format,
674 .subresourceRange = {
675 .aspectMask = src_res->aspectMask,
676 .baseMipLevel = src_res->mipLevel,
677 .levelCount = 1,
678 .baseArrayLayer = src_array_slice,
679 .layerCount = 1
680 },
681 }, NULL);
682 meta_emit_blit(cmd_buffer,
683 src_image, &src_iview, src_image_layout,
684 src_offset_0, src_offset_1,
685 dst_image, &dst_iview, dst_image_layout,
686 dst_offset_0, dst_offset_1,
687 dst_box,
688 sampler);
689 }
690
691 /* Restore conditional rendering. */
692 cmd_buffer->state.predicating = old_predicating;
693
694 radv_meta_restore(&saved_state, cmd_buffer);
695
696 radv_DestroySampler(radv_device_to_handle(device), sampler,
697 &cmd_buffer->pool->alloc);
698 }
699
radv_CmdBlitImage(VkCommandBuffer commandBuffer,VkImage srcImage,VkImageLayout srcImageLayout,VkImage dstImage,VkImageLayout dstImageLayout,uint32_t regionCount,const VkImageBlit * pRegions,VkFilter filter)700 void radv_CmdBlitImage(
701 VkCommandBuffer commandBuffer,
702 VkImage srcImage,
703 VkImageLayout srcImageLayout,
704 VkImage dstImage,
705 VkImageLayout dstImageLayout,
706 uint32_t regionCount,
707 const VkImageBlit* pRegions,
708 VkFilter filter)
709
710 {
711 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
712 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
713 RADV_FROM_HANDLE(radv_image, dst_image, dstImage);
714
715 for (unsigned r = 0; r < regionCount; r++) {
716 VkImageBlit2KHR blit = {
717 .sType = VK_STRUCTURE_TYPE_IMAGE_BLIT_2_KHR,
718 .srcSubresource = pRegions[r].srcSubresource,
719 .srcOffsets = {
720 pRegions[r].srcOffsets[0],
721 pRegions[r].srcOffsets[1],
722 },
723 .dstSubresource = pRegions[r].dstSubresource,
724 .dstOffsets = {
725 pRegions[r].dstOffsets[0],
726 pRegions[r].dstOffsets[1],
727 },
728 };
729
730 blit_image(cmd_buffer,
731 src_image, srcImageLayout,
732 dst_image, dstImageLayout,
733 &blit, filter);
734 }
735 }
736
radv_CmdBlitImage2KHR(VkCommandBuffer commandBuffer,const VkBlitImageInfo2KHR * pBlitImageInfo)737 void radv_CmdBlitImage2KHR(
738 VkCommandBuffer commandBuffer,
739 const VkBlitImageInfo2KHR* pBlitImageInfo)
740 {
741 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
742 RADV_FROM_HANDLE(radv_image, src_image, pBlitImageInfo->srcImage);
743 RADV_FROM_HANDLE(radv_image, dst_image, pBlitImageInfo->dstImage);
744
745 for (unsigned r = 0; r < pBlitImageInfo->regionCount; r++) {
746 blit_image(cmd_buffer,
747 src_image, pBlitImageInfo->srcImageLayout,
748 dst_image, pBlitImageInfo->dstImageLayout,
749 &pBlitImageInfo->pRegions[r],
750 pBlitImageInfo->filter);
751 }
752 }
753
754 void
radv_device_finish_meta_blit_state(struct radv_device * device)755 radv_device_finish_meta_blit_state(struct radv_device *device)
756 {
757 struct radv_meta_state *state = &device->meta_state;
758
759 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
760 for (unsigned j = 0; j < RADV_META_DST_LAYOUT_COUNT; ++j) {
761 radv_DestroyRenderPass(radv_device_to_handle(device),
762 state->blit.render_pass[i][j],
763 &state->alloc);
764 }
765 radv_DestroyPipeline(radv_device_to_handle(device),
766 state->blit.pipeline_1d_src[i],
767 &state->alloc);
768 radv_DestroyPipeline(radv_device_to_handle(device),
769 state->blit.pipeline_2d_src[i],
770 &state->alloc);
771 radv_DestroyPipeline(radv_device_to_handle(device),
772 state->blit.pipeline_3d_src[i],
773 &state->alloc);
774 }
775
776 for (enum radv_blit_ds_layout i = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; i < RADV_BLIT_DS_LAYOUT_COUNT; i++) {
777 radv_DestroyRenderPass(radv_device_to_handle(device),
778 state->blit.depth_only_rp[i], &state->alloc);
779 radv_DestroyRenderPass(radv_device_to_handle(device),
780 state->blit.stencil_only_rp[i], &state->alloc);
781 }
782
783 radv_DestroyPipeline(radv_device_to_handle(device),
784 state->blit.depth_only_1d_pipeline, &state->alloc);
785 radv_DestroyPipeline(radv_device_to_handle(device),
786 state->blit.depth_only_2d_pipeline, &state->alloc);
787 radv_DestroyPipeline(radv_device_to_handle(device),
788 state->blit.depth_only_3d_pipeline, &state->alloc);
789
790 radv_DestroyPipeline(radv_device_to_handle(device),
791 state->blit.stencil_only_1d_pipeline,
792 &state->alloc);
793 radv_DestroyPipeline(radv_device_to_handle(device),
794 state->blit.stencil_only_2d_pipeline,
795 &state->alloc);
796 radv_DestroyPipeline(radv_device_to_handle(device),
797 state->blit.stencil_only_3d_pipeline,
798 &state->alloc);
799
800
801 radv_DestroyPipelineLayout(radv_device_to_handle(device),
802 state->blit.pipeline_layout, &state->alloc);
803 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
804 state->blit.ds_layout, &state->alloc);
805 }
806
807 static VkResult
build_pipeline(struct radv_device * device,VkImageAspectFlagBits aspect,enum glsl_sampler_dim tex_dim,unsigned fs_key,VkPipeline * pipeline)808 build_pipeline(struct radv_device *device,
809 VkImageAspectFlagBits aspect,
810 enum glsl_sampler_dim tex_dim,
811 unsigned fs_key,
812 VkPipeline *pipeline)
813 {
814 VkResult result = VK_SUCCESS;
815
816 mtx_lock(&device->meta_state.mtx);
817
818 if (*pipeline) {
819 mtx_unlock(&device->meta_state.mtx);
820 return VK_SUCCESS;
821 }
822
823 struct radv_shader_module fs = {0};
824 struct radv_shader_module vs = {.nir = build_nir_vertex_shader()};
825 VkRenderPass rp;
826
827 switch(aspect) {
828 case VK_IMAGE_ASPECT_COLOR_BIT:
829 fs.nir = build_nir_copy_fragment_shader(tex_dim);
830 rp = device->meta_state.blit.render_pass[fs_key][0];
831 break;
832 case VK_IMAGE_ASPECT_DEPTH_BIT:
833 fs.nir = build_nir_copy_fragment_shader_depth(tex_dim);
834 rp = device->meta_state.blit.depth_only_rp[0];
835 break;
836 case VK_IMAGE_ASPECT_STENCIL_BIT:
837 fs.nir = build_nir_copy_fragment_shader_stencil(tex_dim);
838 rp = device->meta_state.blit.stencil_only_rp[0];
839 break;
840 default:
841 unreachable("Unhandled aspect");
842 }
843 VkPipelineVertexInputStateCreateInfo vi_create_info = {
844 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
845 .vertexBindingDescriptionCount = 0,
846 .vertexAttributeDescriptionCount = 0,
847 };
848
849 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
850 {
851 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
852 .stage = VK_SHADER_STAGE_VERTEX_BIT,
853 .module = radv_shader_module_to_handle(&vs),
854 .pName = "main",
855 .pSpecializationInfo = NULL
856 }, {
857 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
858 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
859 .module = radv_shader_module_to_handle(&fs),
860 .pName = "main",
861 .pSpecializationInfo = NULL
862 },
863 };
864
865 VkGraphicsPipelineCreateInfo vk_pipeline_info = {
866 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
867 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
868 .pStages = pipeline_shader_stages,
869 .pVertexInputState = &vi_create_info,
870 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
871 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
872 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
873 .primitiveRestartEnable = false,
874 },
875 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
876 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
877 .viewportCount = 1,
878 .scissorCount = 1,
879 },
880 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
881 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
882 .rasterizerDiscardEnable = false,
883 .polygonMode = VK_POLYGON_MODE_FILL,
884 .cullMode = VK_CULL_MODE_NONE,
885 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
886 },
887 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
888 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
889 .rasterizationSamples = 1,
890 .sampleShadingEnable = false,
891 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
892 },
893 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
894 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
895 .dynamicStateCount = 4,
896 .pDynamicStates = (VkDynamicState[]) {
897 VK_DYNAMIC_STATE_VIEWPORT,
898 VK_DYNAMIC_STATE_SCISSOR,
899 VK_DYNAMIC_STATE_LINE_WIDTH,
900 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
901 },
902 },
903 .flags = 0,
904 .layout = device->meta_state.blit.pipeline_layout,
905 .renderPass = rp,
906 .subpass = 0,
907 };
908
909 VkPipelineColorBlendStateCreateInfo color_blend_info = {
910 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
911 .attachmentCount = 1,
912 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
913 {
914 .colorWriteMask = VK_COLOR_COMPONENT_A_BIT |
915 VK_COLOR_COMPONENT_R_BIT |
916 VK_COLOR_COMPONENT_G_BIT |
917 VK_COLOR_COMPONENT_B_BIT },
918 }
919 };
920
921 VkPipelineDepthStencilStateCreateInfo depth_info = {
922 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
923 .depthTestEnable = true,
924 .depthWriteEnable = true,
925 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
926 };
927
928 VkPipelineDepthStencilStateCreateInfo stencil_info = {
929 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
930 .depthTestEnable = false,
931 .depthWriteEnable = false,
932 .stencilTestEnable = true,
933 .front = {
934 .failOp = VK_STENCIL_OP_REPLACE,
935 .passOp = VK_STENCIL_OP_REPLACE,
936 .depthFailOp = VK_STENCIL_OP_REPLACE,
937 .compareOp = VK_COMPARE_OP_ALWAYS,
938 .compareMask = 0xff,
939 .writeMask = 0xff,
940 .reference = 0
941 },
942 .back = {
943 .failOp = VK_STENCIL_OP_REPLACE,
944 .passOp = VK_STENCIL_OP_REPLACE,
945 .depthFailOp = VK_STENCIL_OP_REPLACE,
946 .compareOp = VK_COMPARE_OP_ALWAYS,
947 .compareMask = 0xff,
948 .writeMask = 0xff,
949 .reference = 0
950 },
951 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
952 };
953
954 switch(aspect) {
955 case VK_IMAGE_ASPECT_COLOR_BIT:
956 vk_pipeline_info.pColorBlendState = &color_blend_info;
957 break;
958 case VK_IMAGE_ASPECT_DEPTH_BIT:
959 vk_pipeline_info.pDepthStencilState = &depth_info;
960 break;
961 case VK_IMAGE_ASPECT_STENCIL_BIT:
962 vk_pipeline_info.pDepthStencilState = &stencil_info;
963 break;
964 default:
965 unreachable("Unhandled aspect");
966 }
967
968 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
969 .use_rectlist = true
970 };
971
972 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
973 radv_pipeline_cache_to_handle(&device->meta_state.cache),
974 &vk_pipeline_info, &radv_pipeline_info,
975 &device->meta_state.alloc, pipeline);
976 ralloc_free(vs.nir);
977 ralloc_free(fs.nir);
978 mtx_unlock(&device->meta_state.mtx);
979 return result;
980 }
981
982 static VkResult
radv_device_init_meta_blit_color(struct radv_device * device,bool on_demand)983 radv_device_init_meta_blit_color(struct radv_device *device, bool on_demand)
984 {
985 VkResult result;
986
987 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
988 unsigned key = radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]);
989 for(unsigned j = 0; j < RADV_META_DST_LAYOUT_COUNT; ++j) {
990 VkImageLayout layout = radv_meta_dst_layout_to_layout(j);
991 result = radv_CreateRenderPass(radv_device_to_handle(device),
992 &(VkRenderPassCreateInfo) {
993 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
994 .attachmentCount = 1,
995 .pAttachments = &(VkAttachmentDescription) {
996 .format = radv_fs_key_format_exemplars[i],
997 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
998 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
999 .initialLayout = layout,
1000 .finalLayout = layout,
1001 },
1002 .subpassCount = 1,
1003 .pSubpasses = &(VkSubpassDescription) {
1004 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1005 .inputAttachmentCount = 0,
1006 .colorAttachmentCount = 1,
1007 .pColorAttachments = &(VkAttachmentReference) {
1008 .attachment = 0,
1009 .layout = layout,
1010 },
1011 .pResolveAttachments = NULL,
1012 .pDepthStencilAttachment = &(VkAttachmentReference) {
1013 .attachment = VK_ATTACHMENT_UNUSED,
1014 .layout = VK_IMAGE_LAYOUT_GENERAL,
1015 },
1016 .preserveAttachmentCount = 0,
1017 .pPreserveAttachments = NULL,
1018 },
1019 .dependencyCount = 2,
1020 .pDependencies = (VkSubpassDependency[]) {
1021 {
1022 .srcSubpass = VK_SUBPASS_EXTERNAL,
1023 .dstSubpass = 0,
1024 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1025 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1026 .srcAccessMask = 0,
1027 .dstAccessMask = 0,
1028 .dependencyFlags = 0
1029 },
1030 {
1031 .srcSubpass = 0,
1032 .dstSubpass = VK_SUBPASS_EXTERNAL,
1033 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1034 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1035 .srcAccessMask = 0,
1036 .dstAccessMask = 0,
1037 .dependencyFlags = 0
1038 }
1039 },
1040 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key][j]);
1041 if (result != VK_SUCCESS)
1042 goto fail;
1043 }
1044
1045 if (on_demand)
1046 continue;
1047
1048 result = build_pipeline(device, VK_IMAGE_ASPECT_COLOR_BIT, GLSL_SAMPLER_DIM_1D, key, &device->meta_state.blit.pipeline_1d_src[key]);
1049 if (result != VK_SUCCESS)
1050 goto fail;
1051
1052 result = build_pipeline(device, VK_IMAGE_ASPECT_COLOR_BIT, GLSL_SAMPLER_DIM_2D, key, &device->meta_state.blit.pipeline_2d_src[key]);
1053 if (result != VK_SUCCESS)
1054 goto fail;
1055
1056 result = build_pipeline(device, VK_IMAGE_ASPECT_COLOR_BIT, GLSL_SAMPLER_DIM_3D, key, &device->meta_state.blit.pipeline_3d_src[key]);
1057 if (result != VK_SUCCESS)
1058 goto fail;
1059
1060 }
1061
1062 result = VK_SUCCESS;
1063 fail:
1064 return result;
1065 }
1066
1067 static VkResult
radv_device_init_meta_blit_depth(struct radv_device * device,bool on_demand)1068 radv_device_init_meta_blit_depth(struct radv_device *device, bool on_demand)
1069 {
1070 VkResult result;
1071
1072 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1073 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1074 result = radv_CreateRenderPass(radv_device_to_handle(device),
1075 &(VkRenderPassCreateInfo) {
1076 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1077 .attachmentCount = 1,
1078 .pAttachments = &(VkAttachmentDescription) {
1079 .format = VK_FORMAT_D32_SFLOAT,
1080 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1081 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1082 .initialLayout = layout,
1083 .finalLayout = layout,
1084 },
1085 .subpassCount = 1,
1086 .pSubpasses = &(VkSubpassDescription) {
1087 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1088 .inputAttachmentCount = 0,
1089 .colorAttachmentCount = 0,
1090 .pColorAttachments = NULL,
1091 .pResolveAttachments = NULL,
1092 .pDepthStencilAttachment = &(VkAttachmentReference) {
1093 .attachment = 0,
1094 .layout = layout,
1095 },
1096 .preserveAttachmentCount = 0,
1097 .pPreserveAttachments = NULL,
1098 },
1099 .dependencyCount = 2,
1100 .pDependencies = (VkSubpassDependency[]) {
1101 {
1102 .srcSubpass = VK_SUBPASS_EXTERNAL,
1103 .dstSubpass = 0,
1104 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1105 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1106 .srcAccessMask = 0,
1107 .dstAccessMask = 0,
1108 .dependencyFlags = 0
1109 },
1110 {
1111 .srcSubpass = 0,
1112 .dstSubpass = VK_SUBPASS_EXTERNAL,
1113 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1114 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1115 .srcAccessMask = 0,
1116 .dstAccessMask = 0,
1117 .dependencyFlags = 0
1118 }
1119 },
1120 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp[ds_layout]);
1121 if (result != VK_SUCCESS)
1122 goto fail;
1123 }
1124
1125 if (on_demand)
1126 return VK_SUCCESS;
1127
1128 result = build_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, GLSL_SAMPLER_DIM_1D, 0, &device->meta_state.blit.depth_only_1d_pipeline);
1129 if (result != VK_SUCCESS)
1130 goto fail;
1131
1132 result = build_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, GLSL_SAMPLER_DIM_2D, 0, &device->meta_state.blit.depth_only_2d_pipeline);
1133 if (result != VK_SUCCESS)
1134 goto fail;
1135
1136 result = build_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, GLSL_SAMPLER_DIM_3D, 0, &device->meta_state.blit.depth_only_3d_pipeline);
1137 if (result != VK_SUCCESS)
1138 goto fail;
1139
1140 fail:
1141 return result;
1142 }
1143
1144 static VkResult
radv_device_init_meta_blit_stencil(struct radv_device * device,bool on_demand)1145 radv_device_init_meta_blit_stencil(struct radv_device *device, bool on_demand)
1146 {
1147 VkResult result;
1148
1149 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
1150 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1151 result = radv_CreateRenderPass(radv_device_to_handle(device),
1152 &(VkRenderPassCreateInfo) {
1153 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1154 .attachmentCount = 1,
1155 .pAttachments = &(VkAttachmentDescription) {
1156 .format = VK_FORMAT_S8_UINT,
1157 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1158 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1159 .initialLayout = layout,
1160 .finalLayout = layout,
1161 },
1162 .subpassCount = 1,
1163 .pSubpasses = &(VkSubpassDescription) {
1164 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1165 .inputAttachmentCount = 0,
1166 .colorAttachmentCount = 0,
1167 .pColorAttachments = NULL,
1168 .pResolveAttachments = NULL,
1169 .pDepthStencilAttachment = &(VkAttachmentReference) {
1170 .attachment = 0,
1171 .layout = layout,
1172 },
1173 .preserveAttachmentCount = 0,
1174 .pPreserveAttachments = NULL,
1175 },
1176 .dependencyCount = 2,
1177 .pDependencies = (VkSubpassDependency[]) {
1178 {
1179 .srcSubpass = VK_SUBPASS_EXTERNAL,
1180 .dstSubpass = 0,
1181 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1182 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1183 .srcAccessMask = 0,
1184 .dstAccessMask = 0,
1185 .dependencyFlags = 0
1186 },
1187 {
1188 .srcSubpass = 0,
1189 .dstSubpass = VK_SUBPASS_EXTERNAL,
1190 .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
1191 .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
1192 .srcAccessMask = 0,
1193 .dstAccessMask = 0,
1194 .dependencyFlags = 0
1195 }
1196 },
1197
1198 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp[ds_layout]);
1199 }
1200 if (result != VK_SUCCESS)
1201 goto fail;
1202
1203 if (on_demand)
1204 return VK_SUCCESS;
1205
1206 result = build_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, GLSL_SAMPLER_DIM_1D, 0, &device->meta_state.blit.stencil_only_1d_pipeline);
1207 if (result != VK_SUCCESS)
1208 goto fail;
1209
1210 result = build_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, GLSL_SAMPLER_DIM_2D, 0, &device->meta_state.blit.stencil_only_2d_pipeline);
1211 if (result != VK_SUCCESS)
1212 goto fail;
1213
1214 result = build_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, GLSL_SAMPLER_DIM_3D, 0, &device->meta_state.blit.stencil_only_3d_pipeline);
1215 if (result != VK_SUCCESS)
1216 goto fail;
1217
1218
1219 fail:
1220 return result;
1221 }
1222
1223 VkResult
radv_device_init_meta_blit_state(struct radv_device * device,bool on_demand)1224 radv_device_init_meta_blit_state(struct radv_device *device, bool on_demand)
1225 {
1226 VkResult result;
1227
1228 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1229 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1230 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1231 .bindingCount = 1,
1232 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1233 {
1234 .binding = 0,
1235 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1236 .descriptorCount = 1,
1237 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1238 .pImmutableSamplers = NULL
1239 },
1240 }
1241 };
1242 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1243 &ds_layout_info,
1244 &device->meta_state.alloc,
1245 &device->meta_state.blit.ds_layout);
1246 if (result != VK_SUCCESS)
1247 goto fail;
1248
1249 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1250
1251 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1252 &(VkPipelineLayoutCreateInfo) {
1253 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1254 .setLayoutCount = 1,
1255 .pSetLayouts = &device->meta_state.blit.ds_layout,
1256 .pushConstantRangeCount = 1,
1257 .pPushConstantRanges = &push_constant_range,
1258 },
1259 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1260 if (result != VK_SUCCESS)
1261 goto fail;
1262
1263 result = radv_device_init_meta_blit_color(device, on_demand);
1264 if (result != VK_SUCCESS)
1265 goto fail;
1266
1267 result = radv_device_init_meta_blit_depth(device, on_demand);
1268 if (result != VK_SUCCESS)
1269 goto fail;
1270
1271 result = radv_device_init_meta_blit_stencil(device, on_demand);
1272
1273 fail:
1274 if (result != VK_SUCCESS)
1275 radv_device_finish_meta_blit_state(device);
1276 return result;
1277 }
1278