| /external/iproute2/rdma/ |
| D | link.c | 14 static int link_help(struct rd *rd) in link_help() argument
16 pr_out("Usage: %s link show [DEV/PORT_INDEX]\n", rd->filename); in link_help()
59 static void link_print_caps(struct rd *rd, struct nlattr **tb) in link_print_caps() argument
69 if (rd->json_output) { in link_print_caps()
70 jsonw_name(rd->jw, "caps"); in link_print_caps()
71 jsonw_start_array(rd->jw); in link_print_caps()
77 if (rd->json_output) { in link_print_caps()
78 jsonw_string(rd->jw, caps_to_str(idx)); in link_print_caps()
88 if (rd->json_output) in link_print_caps()
89 jsonw_end_array(rd->jw); in link_print_caps()
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| D | utils.c | 14 static int rd_argc(struct rd *rd) in rd_argc() argument
16 return rd->argc; in rd_argc()
19 char *rd_argv(struct rd *rd) in rd_argv() argument
21 if (!rd_argc(rd)) in rd_argv()
23 return *rd->argv; in rd_argv()
33 static bool rd_argv_match(struct rd *rd, const char *pattern) in rd_argv_match() argument
35 if (!rd_argc(rd)) in rd_argv_match()
37 return strcmpx(rd_argv(rd), pattern) == 0; in rd_argv_match()
40 void rd_arg_inc(struct rd *rd) in rd_arg_inc() argument
42 if (!rd_argc(rd)) in rd_arg_inc()
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| D | dev.c | 14 static int dev_help(struct rd *rd) in dev_help() argument
16 pr_out("Usage: %s dev show [DEV]\n", rd->filename); in dev_help()
69 static void dev_print_caps(struct rd *rd, struct nlattr **tb) in dev_print_caps() argument
79 if (rd->json_output) { in dev_print_caps()
80 jsonw_name(rd->jw, "caps"); in dev_print_caps()
81 jsonw_start_array(rd->jw); in dev_print_caps()
87 if (rd->json_output) { in dev_print_caps()
88 jsonw_string(rd->jw, dev_caps_to_str(idx)); in dev_print_caps()
98 if (rd->json_output) in dev_print_caps()
99 jsonw_end_array(rd->jw); in dev_print_caps()
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| D | rdma.c | 22 static int cmd_help(struct rd *rd) in cmd_help() argument
24 help(rd->filename); in cmd_help()
28 static int rd_cmd(struct rd *rd) in rd_cmd() argument
38 return rd_exec_cmd(rd, cmds, "object"); in rd_cmd()
41 static int rd_init(struct rd *rd, int argc, char **argv, char *filename) in rd_init() argument
46 rd->filename = filename; in rd_init()
47 rd->argc = argc; in rd_init()
48 rd->argv = argv; in rd_init()
49 INIT_LIST_HEAD(&rd->dev_map_list); in rd_init()
51 if (rd->json_output) { in rd_init()
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| D | rdma.h | 39 struct rd { struct
57 int (*func)(struct rd *rd); argument
63 bool rd_no_arg(struct rd *rd);
64 void rd_arg_inc(struct rd *rd);
66 char *rd_argv(struct rd *rd);
67 uint32_t get_port_from_argv(struct rd *rd);
72 int cmd_dev(struct rd *rd);
73 int cmd_link(struct rd *rd);
74 int rd_exec_cmd(struct rd *rd, const struct rd_cmd *c, const char *str);
79 void rd_free_devmap(struct rd *rd);
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 555 void Adr(Condition cond, Register rd, RawLiteral* literal) { in Adr() argument
556 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); in Adr()
563 bool can_encode = adr_info(cond, Best, rd, literal, &info); in Adr()
571 adr(cond, Best, rd, literal); in Adr()
574 void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); } in Adr() argument
707 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) { in Vldr() argument
708 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); in Vldr()
715 bool can_encode = vldr_info(cond, dt, rd, literal, &info); in Vldr()
723 vldr(cond, dt, rd, literal); in Vldr()
726 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) { in Vldr() argument
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| D | assembler-aarch32.h | 246 Register rd,
250 Register rd,
252 typedef void (Assembler::*InstructionROp)(Register rd,
255 Register rd,
260 Register rd,
263 QRegister rd,
269 Register rd,
273 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width);
281 Register rd,
288 Register rd,
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| D | disasm-aarch32.h | 612 Register rd,
618 Register rd,
624 Register rd,
628 void add(Condition cond, Register rd, const Operand& operand);
632 Register rd,
636 void adds(Register rd, const Operand& operand);
638 void addw(Condition cond, Register rd, Register rn, const Operand& operand);
640 void adr(Condition cond, EncodingSize size, Register rd, Location* location);
644 Register rd,
650 Register rd,
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| D | disasm-aarch32.cc | 1129 Register rd, in adc() argument
1135 if (!rd.Is(rn) || !use_short_hand_form_) { in adc()
1136 os() << rd << ", "; in adc()
1143 Register rd, in adcs() argument
1149 if (!rd.Is(rn) || !use_short_hand_form_) { in adcs()
1150 os() << rd << ", "; in adcs()
1157 Register rd, in add() argument
1163 if (!rd.Is(rn) || !use_short_hand_form_) { in add()
1164 os() << rd << ", "; in add()
1169 void Disassembler::add(Condition cond, Register rd, const Operand& operand) { in add() argument
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| D | assembler-aarch32.cc | 1925 Register rd, in adc() argument
1936 ((!rd.IsPC() && !rn.IsPC()) || AllowUnpredictable())) { in adc()
1937 EmitT32_32(0xf1400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc()
1949 (rd.GetCode() << 12) | (rn.GetCode() << 16) | in adc()
1960 if (InITBlock() && !size.IsWide() && rd.Is(rn) && rn.IsLow() && in adc()
1962 EmitT32_16(0x4140 | rd.GetCode() | (rm.GetCode() << 3)); in adc()
1973 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC()) || AllowUnpredictable())) { in adc()
1975 EmitT32_32(0xeb400000U | (rd.GetCode() << 8) | (rn.GetCode() << 16) | in adc()
1986 (rd.GetCode() << 12) | (rn.GetCode() << 16) | rm.GetCode() | in adc()
1999 ((!rd.IsPC() && !rn.IsPC() && !rm.IsPC() && !rs.IsPC()) || in adc()
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| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 1 { /* AArch64_ABSv16i8, ARM64_INS_ABS: abs.16b $rd, $rn */
5 { /* AArch64_ABSv1i64, ARM64_INS_ABS: abs $rd, $rn */
9 { /* AArch64_ABSv2i32, ARM64_INS_ABS: abs.2s $rd, $rn */
13 { /* AArch64_ABSv2i64, ARM64_INS_ABS: abs.2d $rd, $rn */
17 { /* AArch64_ABSv4i16, ARM64_INS_ABS: abs.4h $rd, $rn */
21 { /* AArch64_ABSv4i32, ARM64_INS_ABS: abs.4s $rd, $rn */
25 { /* AArch64_ABSv8i16, ARM64_INS_ABS: abs.8h $rd, $rn */
29 { /* AArch64_ABSv8i8, ARM64_INS_ABS: abs.8b $rd, $rn */
33 { /* AArch64_ADCSWr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */
37 { /* AArch64_ADCSXr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 15 // mov<cond> <ccreg> rs2, rd
20 // mov<cond> (%icc|%xcc), rs2, rd
22 ", $rs2, $rd"),
23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
25 // mov<cond> (%icc|%xcc), simm11, rd
27 ", $simm11, $rd"),
28 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
30 // fmovs<cond> (%icc|%xcc), $rs2, $rd
32 ", $rs2, $rd"),
33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
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| D | SparcInstrVIS.td | 21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
31 let rd = 0, rs1 = 0, rs2 = 0 in
35 // For VIS Instructions with only rs1, rd operands.
39 (outs RC:$rd), (ins RC:$rs1),
40 !strconcat(OpcStr, " $rs1, $rd"), []>;
42 // For VIS Instructions with only rs2, rd operands.
46 (outs RC:$rd), (ins RC:$rs2),
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 14 // mov<cond> <ccreg> rs2, rd
19 // mov<cond> (%icc|%xcc), rs2, rd
21 ", $rs2, $rd"),
22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
24 // mov<cond> (%icc|%xcc), simm11, rd
26 ", $simm11, $rd"),
27 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
29 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 ", $rs2, $rd"),
32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
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| D | SparcInstrVIS.td | 20 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
26 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
30 let rd = 0, rs1 = 0, rs2 = 0 in
34 // For VIS Instructions with only rs1, rd operands.
38 (outs RC:$rd), (ins RC:$rs1),
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
41 // For VIS Instructions with only rs2, rd operands.
45 (outs RC:$rd), (ins RC:$rs2),
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 14 // mov<cond> <ccreg> rs2, rd
19 // mov<cond> (%icc|%xcc), rs2, rd
21 ", $rs2, $rd"),
22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
24 // mov<cond> (%icc|%xcc), simm11, rd
26 ", $simm11, $rd"),
27 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
29 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 ", $rs2, $rd"),
32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
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| D | SparcInstrVIS.td | 20 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
26 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
30 let rd = 0, rs1 = 0, rs2 = 0 in
34 // For VIS Instructions with only rs1, rd operands.
38 (outs RC:$rd), (ins RC:$rs1),
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
41 // For VIS Instructions with only rs2, rd operands.
45 (outs RC:$rd), (ins RC:$rs2),
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| /external/libaom/libaom/av1/encoder/ |
| D | rd.c | 450 static void set_block_thresholds(const AV1_COMMON *cm, RD_OPT *rd) { in set_block_thresholds() argument
467 rd->threshes[segment_id][bsize][i] = rd->thresh_mult[i] < thresh_max in set_block_thresholds()
468 ? rd->thresh_mult[i] * t / 4 in set_block_thresholds()
588 RD_OPT *const rd = &cpi->rd; in av1_initialize_rd_consts() local
592 rd->RDMULT = av1_compute_rd_mult( in av1_initialize_rd_consts()
595 set_error_per_bit(x, rd->RDMULT); in av1_initialize_rd_consts()
597 set_block_thresholds(cm, rd); in av1_initialize_rd_consts()
1091 RD_OPT *const rd = &cpi->rd; in av1_set_rd_speed_thresholds() local
1094 av1_zero(rd->thresh_mult); in av1_set_rd_speed_thresholds()
1096 rd->thresh_mult[THR_NEARESTMV] = 300; in av1_set_rd_speed_thresholds()
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| /external/llvm-project/clang/test/Analysis/ |
| D | cfg-openmp.cpp | 13 int x, cond, fp, rd, lin, step, map; in xxx() local
49 #pragma omp parallel if(cond) firstprivate(fp) reduction(min:rd) in xxx()
64 #pragma omp parallel sections if(cond) firstprivate(fp) reduction(&&:rd) in xxx()
91 : argc) if(cond) firstprivate(fp) reduction(-:rd) in xxx()
108 #pragma omp target parallel if(cond) firstprivate(fp) reduction(+:rd) map(to:map) in xxx()
125 #pragma omp target teams if(cond) firstprivate(fp) reduction(+:rd) map(tofrom:map) in xxx()
169 #pragma omp teams firstprivate(fp) reduction(+:rd) in xxx()
176 int x, cond, fp, rd, lin, step, map; in dpf() local
191 #pragma omp distribute parallel for if(parallel:cond) firstprivate(fp) reduction(+:rd) in dpf()
198 int x, cond, fp, rd, lin, step, map; in dpfs() local
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| /external/python/cpython3/Lib/test/ |
| D | test_selectors.py | 54 rd, wr = socketpair()
55 self.addCleanup(rd.close)
57 return rd, wr
63 rd, wr = self.make_socketpair()
65 key = s.register(rd, selectors.EVENT_READ, "data")
67 self.assertEqual(key.fileobj, rd)
68 self.assertEqual(key.fd, rd.fileno())
79 self.assertRaises(KeyError, s.register, rd, selectors.EVENT_READ)
82 self.assertRaises(KeyError, s.register, rd.fileno(),
89 rd, wr = self.make_socketpair()
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| /external/llvm-project/llvm/test/CodeGen/NVPTX/ |
| D | load-store.ll | 5 ; CHECK: ld.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
8 ; CHECK: st.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
11 ; CHECK: ld.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
14 ; CHECK: st.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
17 ; CHECK: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
20 ; CHECK: st.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
23 ; CHECK: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
26 ; CHECK: st.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
34 ; CHECK: ld.volatile.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
37 ; CHECK: st.volatile.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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| /external/perfetto/src/profiling/memory/ |
| D | shared_ring_buffer_unittest.cc | 52 void StructuredTest(SharedRingBuffer* wr, SharedRingBuffer* rd) { in StructuredTest() argument
55 ASSERT_TRUE(wr->size() == rd->size()); in StructuredTest()
63 auto buf_and_size = rd->BeginRead(); in StructuredTest()
66 rd->EndRead(std::move(buf_and_size)); in StructuredTest()
69 auto buf_and_size = rd->BeginRead(); in StructuredTest()
72 rd->EndRead(std::move(buf_and_size)); in StructuredTest()
76 auto buf_and_size = rd->BeginRead(); in StructuredTest()
90 auto buf_and_size = rd->BeginRead(); in StructuredTest()
92 rd->EndRead(std::move(buf_and_size)); in StructuredTest()
100 auto buf_and_size = rd->BeginRead(); in StructuredTest()
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| /external/icu/icu4c/source/test/cintltst/ |
| D | uregiontest.c | 362 const KnownRegion * rd; in TestKnownRegions() local
363 for (rd = knownRegions; rd->code != NULL ; rd++ ) { in TestKnownRegions()
365 const URegion *r = uregion_getRegionFromCode(rd->code, &status); in TestKnownRegions()
368 int32_t e = rd->numeric; in TestKnownRegions()
372 if (uregion_getType(r) != rd->type) { in TestKnownRegions()
373 …Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getTy… in TestKnownRegions()
383 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code); in TestKnownRegions()
389 const KnownRegion * rd; in TestGetContainedRegions() local
390 for (rd = knownRegions; rd->code != NULL ; rd++ ) { in TestGetContainedRegions()
392 const URegion *r = uregion_getRegionFromCode(rd->code, &status); in TestGetContainedRegions()
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_sched_gm107.h | 17 } rd, wr; member
28 rd.r[i] += delta; in rebase()
32 rd.p[i] += delta; in rebase()
35 rd.c += delta; in rebase()
40 memset(&rd, 0, sizeof(rd)); in wipe()
58 return getLatest(rd); in getLatestRd()
71 rd.r[i] = MAX2(rd.r[i], that->rd.r[i]); in setMax()
75 rd.p[i] = MAX2(rd.p[i], that->rd.p[i]); in setMax()
78 rd.c = MAX2(rd.c, that->rd.c); in setMax()
84 if (rd.r[i] > cycle) in print()
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoB.td | 110 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
111 opcodestr, "$rd, $rs1"> {
117 : RVInstI<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
118 (ins GPR:$rs1, simm12:$imm12), opcodestr, "$rd, $rs1, $imm12">;
123 : RVInstI<funct3, opcode, (outs GPR:$rd),
125 "$rd, $rs1, $shamt"> {
139 : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$shamt),
140 opcodestr, "$rd, $rs1, $shamt"> {
150 : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, shfl_uimm:$shamt),
151 opcodestr, "$rd, $rs1, $shamt"> {
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