/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | sve-intrinsics-ffr-manipulation.ll | 11 define <vscale x 16 x i1> @rdffr() { 12 ; CHECK-LABEL: rdffr: 13 ; CHECK: rdffr p0.b 15 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 21 ; CHECK: rdffr p0.b, p0/z 23 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> %pg) 51 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr() 52 declare <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1>)
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/external/llvm-project/llvm/test/MC/AArch64/SVE/ |
D | rdffr.s | 10 rdffr p0.b label 16 rdffr p15.b label 22 rdffr p0.b, p0/z label 28 rdffr p15.b, p15/z label
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D | rdffr-diagnostics.s | 6 rdffr p0.h label 11 rdffr p0.s label 16 rdffr p0.d label
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SVEInstrInfo.td | 81 def RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr">; 83 def RDFFR_P : sve_int_rdffr_unpred<"rdffr">;
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.h | 5159 void rdffr(const PRegisterWithLaneSize& pd); 5162 void rdffr(const PRegisterWithLaneSize& pd, const PRegisterZ& pg);
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D | assembler-sve-aarch64.cc | 6191 void Assembler::rdffr(const PRegisterWithLaneSize& pd) { in rdffr() function in vixl::aarch64::Assembler 6201 void Assembler::rdffr(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) { in rdffr() function in vixl::aarch64::Assembler
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D | macro-assembler-aarch64.h | 5557 rdffr(pd.VnB()); in Rdffr() 5562 rdffr(pd, pg); in Rdffr()
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64SVEInstrInfo.td | 273 defm RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr", int_aarch64_sve_rdffr_z>; 275 defm RDFFR_P : sve_int_rdffr_unpred<"rdffr", int_aarch64_sve_rdffr>;
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/external/vixl/test/aarch64/ |
D | test-disasm-sve-aarch64.cc | 6215 COMPARE_PREFIX(rdffr(p13.VnB()), "rdffr p13.b"); in TEST() 6217 COMPARE_PREFIX(rdffr(p5.VnB(), p14.Zeroing()), "rdffr p5.b, p14/z"); in TEST()
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenAsmMatcher.inc | 17009 …{ 3785 /* rdffr */, AArch64::RDFFR_P, Convert__SVEPredicateBReg1_0, AMFBS_HasSVE, { MCK_SVEPredica… 17010 …{ 3785 /* rdffr */, AArch64::RDFFR_PPz, Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1, AMFBS… 24382 …{ 3785 /* rdffr */, AArch64::RDFFR_P, Convert__SVEPredicateBReg1_0, AMFBS_HasSVE, { MCK_SVEPredica… 24383 …{ 3785 /* rdffr */, AArch64::RDFFR_PPz, Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1, AMFBS… 35875 { 3785 /* rdffr */, 1 /* 0 */, MCK_SVEPredicateBReg, AMFBS_HasSVE }, 35876 { 3785 /* rdffr */, 1 /* 0 */, MCK_SVEPredicateBReg, AMFBS_HasSVE }, 35877 { 3785 /* rdffr */, 1 /* 0 */, MCK_SVEPredicateBReg, AMFBS_HasSVE }, 35878 { 3785 /* rdffr */, 2 /* 1 */, MCK_SVEPredicateAnyReg, AMFBS_HasSVE }, 35879 { 3785 /* rdffr */, 1 /* 0 */, MCK_SVEPredicateBReg, AMFBS_HasSVE }, 35880 { 3785 /* rdffr */, 2 /* 1 */, MCK_SVEPredicateAnyReg, AMFBS_HasSVE },
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