| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
49 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
52 DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3); in idct32x8_row_even_process_store()
53 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
66 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
68 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3); in idct32x8_row_even_process_store()
78 reg5 = reg7 + reg3; in idct32x8_row_even_process_store()
79 reg7 = reg7 - reg3; in idct32x8_row_even_process_store()
80 reg3 = vec0; in idct32x8_row_even_process_store()
83 reg2 = reg3 + reg4; in idct32x8_row_even_process_store()
[all …]
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| D | idct16x16_msa.c | 17 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
20 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
24 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
25 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
50 DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1); in vpx_idct16_1d_rows_msa()
51 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vpx_idct16_1d_rows_msa()
53 loc1 = reg15 + reg3; in vpx_idct16_1d_rows_msa()
54 reg3 = reg15 - reg3; in vpx_idct16_1d_rows_msa()
86 DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13); in vpx_idct16_1d_rows_msa()
87 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
[all …]
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| /external/vixl/src/aarch64/ |
| D | registers-aarch64.cc | 175 const CPURegister& reg3, in AreAliased() argument
189 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
226 const CPURegister& reg3, in AreSameSizeAndType() argument
235 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
246 const CPURegister& reg3, in AreEven() argument
255 even &= !reg3.IsValid() || ((reg3.GetCode() % 2) == 0); in AreEven()
266 const CPURegister& reg3, in AreConsecutive() argument
277 if (!reg3.IsValid()) { in AreConsecutive()
279 } else if (reg3.GetCode() != in AreConsecutive()
287 ((reg3.GetCode() + 1) % (reg1.GetMaxCode() + 1))) { in AreConsecutive()
[all …]
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| D | registers-aarch64.h | 839 const CPURegister& reg3 = NoReg,
852 const CPURegister& reg3 = NoCPUReg,
864 const CPURegister& reg3 = NoReg,
877 const CPURegister& reg3 = NoCPUReg,
885 const CPURegister& reg3 = NoCPUReg,
895 const CPURegister& reg3 = NoCPUReg,
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| /external/libvpx/libvpx/vpx_ports/ |
| D | asmdefs_mmi.h | 21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
22 "daddu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
31 "dsubu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
51 "addu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
60 "subu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 39 ; THUMB: movw r[[reg3:[0-9]+]],
40 ; THUMB: movt r[[reg3]],
41 ; THUMB: add r[[reg3]], pc
42 ; THUMB: ldr r[[reg3]], [r[[reg3]]]
44 ; THUMB-ELF: ldr r[[reg3:[0-9]+]],
45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 39 ; THUMB: movw r[[reg3:[0-9]+]],
40 ; THUMB: movt r[[reg3]],
41 ; THUMB: add r[[reg3]], pc
42 ; THUMB: ldr r[[reg3]], [r[[reg3]]]
44 ; THUMB-ELF: ldr r[[reg3:[0-9]+]],
45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
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| /external/elfutils/tests/ |
| D | run-dwarfcfi.sh | 41 reg3: same_value
58 reg3: undefined
75 reg3: undefined
92 reg3: undefined
109 reg3: undefined
126 reg3: undefined
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| D | run-varlocs.sh | 68 [40051c,40052a) {reg3}
107 [400408,400421) {reg3}
179 [40118e,40119c) {reg3}
181 [4011a7,4011b5) {reg3}
257 [40118e,40119c) {reg3}
259 [4011a7,4011b5) {reg3}
331 [40050e,40051c) {reg3}
333 [400527,400535) {reg3}
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| D | run-readelf-zdebug-rel.sh | 237 [ 0] reg3
243 [ 0] reg3
246 [ 0] reg3
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
93 reg3 = __msa_hadd_u_h(vec3, vec3); in ScaleARGBRowDown2Box_MSA()
95 reg1 += reg3; in ScaleARGBRowDown2Box_MSA()
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
168 reg3 = __msa_hadd_u_h(vec3, vec3); in ScaleARGBRowDownEvenBox_MSA()
170 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
172 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
342 reg3 = __msa_hadd_u_w(vec3, vec3); in ScaleRowDown4Box_MSA()
346 reg3 = (v4u32)__msa_srari_w((v4i32)reg3, 4); in ScaleRowDown4Box_MSA()
[all …]
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
[all …]
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| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
78 reg3 = __msa_dpadd_s_w(reg3, vec3, vec3); in SumSquareError_MSA()
84 reg2 += reg3; in SumSquareError_MSA()
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| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
508 reg3 = (v16u8)__msa_pckev_b((v16i8)vec5, (v16i8)vec2); in I422ToRGB24Row_MSA()
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0); in I422ToRGB24Row_MSA()
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); in I422ToRGB24Row_MSA()
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2); in I422ToRGB24Row_MSA()
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
793 reg3 = (v8u16)__msa_ilvev_b(zero, (v16i8)vec3); in ARGBToYRow_MSA()
799 reg3 *= const_0x81; in ARGBToYRow_MSA()
803 reg1 += reg3; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
[all …]
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| /external/libyuv/files/source/ |
| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
93 reg3 = __msa_hadd_u_h(vec3, vec3); in ScaleARGBRowDown2Box_MSA()
95 reg1 += reg3; in ScaleARGBRowDown2Box_MSA()
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
168 reg3 = __msa_hadd_u_h(vec3, vec3); in ScaleARGBRowDownEvenBox_MSA()
170 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
172 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
342 reg3 = __msa_hadd_u_w(vec3, vec3); in ScaleRowDown4Box_MSA()
346 reg3 = (v4u32)__msa_srari_w((v4i32)reg3, 4); in ScaleRowDown4Box_MSA()
[all …]
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); in TransposeUVWx16_MSA()
[all …]
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| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
78 reg3 = __msa_dpadd_s_w(reg3, vec3, vec3); in SumSquareError_MSA()
84 reg2 += reg3; in SumSquareError_MSA()
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| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
508 reg3 = (v16u8)__msa_pckev_b((v16i8)vec5, (v16i8)vec2); in I422ToRGB24Row_MSA()
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0); in I422ToRGB24Row_MSA()
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); in I422ToRGB24Row_MSA()
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2); in I422ToRGB24Row_MSA()
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
793 reg3 = (v8u16)__msa_ilvev_b(zero, (v16i8)vec3); in ARGBToYRow_MSA()
799 reg3 *= const_0x81; in ARGBToYRow_MSA()
803 reg1 += reg3; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
[all …]
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | pv-packing.ll | 6 … x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
14 %6 = extractelement <4 x float> %reg3, i32 0
15 %7 = extractelement <4 x float> %reg3, i32 1
16 %8 = extractelement <4 x float> %reg3, i32 2
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| D | load-input-fold.ll | 3 … x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
13 %8 = extractelement <4 x float> %reg3, i32 0
14 %9 = extractelement <4 x float> %reg3, i32 1
15 %10 = extractelement <4 x float> %reg3, i32 2
16 %11 = extractelement <4 x float> %reg3, i32 3
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | pv-packing.ll | 6 … x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
14 %6 = extractelement <4 x float> %reg3, i32 0
15 %7 = extractelement <4 x float> %reg3, i32 1
16 %8 = extractelement <4 x float> %reg3, i32 2
|
| D | load-input-fold.ll | 3 … x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) {
13 %8 = extractelement <4 x float> %reg3, i32 0
14 %9 = extractelement <4 x float> %reg3, i32 1
15 %10 = extractelement <4 x float> %reg3, i32 2
16 %11 = extractelement <4 x float> %reg3, i32 3
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| D | pv.ll | 6 …eg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg …
16 %8 = extractelement <4 x float> %reg3, i32 0
17 %9 = extractelement <4 x float> %reg3, i32 1
18 %10 = extractelement <4 x float> %reg3, i32 2
19 %11 = extractelement <4 x float> %reg3, i32 3
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| /external/mesa3d/src/panfrost/bifrost/ |
| D | disassemble.c | 152 else if (regs.reg2 == regs.reg3) in DecodeRegCtrl()
183 fprintf(fp, "slot 3: r%d (write %s) ", srcs.reg3, slot3_fma); in dump_regs()
185 fprintf(fp, "slot 3: r%d (write lo %s) ", srcs.reg3, slot3_fma); in dump_regs()
187 fprintf(fp, "slot 3: r%d (write hi %s) ", srcs.reg3, slot3_fma); in dump_regs()
216 fprintf(fp, "r%u:t0", next_regs->reg3); in bi_disasm_dest_fma()
229 fprintf(fp, "r%u:t1", next_regs->reg3); in bi_disasm_dest_add()
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 465 RegisterList(Register reg1, Register reg2, Register reg3)
467 RegisterToList(reg3)) {}
468 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
470 RegisterToList(reg3) | RegisterToList(reg4)) {}
554 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3) in VRegisterList() argument
556 RegisterToList(reg3)) {} in VRegisterList()
557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4) in VRegisterList() argument
559 RegisterToList(reg3) | RegisterToList(reg4)) {} in VRegisterList()
|