Home
last modified time | relevance | path

Searched refs:reg8 (Results 1 – 23 of 23) sorted by relevance

/external/elfutils/tests/
Drun-dwarfcfi.sh36 return address in reg8
46 reg8: location expression: call_frame_cfa plus_uconst(-4)
63 reg8: undefined
80 reg8: undefined
97 reg8: undefined
114 reg8: same_value
131 reg8: undefined
Drun-addrcfi.sh31 return address in reg8
41 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
78 return address in reg8
88 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
140 integer reg8 (%r8): undefined
206 integer reg8 (%r8): undefined
310 integer reg8 (r8): undefined
1332 integer reg8 (r8): undefined
2360 integer reg8 (r8): undefined
3386 integer reg8 (%r8): same_value
[all …]
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c16 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
22 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
26 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg8, in vpx_idct16_1d_rows_msa()
32 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vpx_idct16_1d_rows_msa()
34 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
36 reg8); in vpx_idct16_1d_rows_msa()
81 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
87 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
97 TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14, reg0, in vpx_idct16_1d_rows_msa()
98 reg2, reg4, reg6, reg8, reg10, reg12, reg14); in vpx_idct16_1d_rows_msa()
[all …]
/external/vixl/src/aarch64/
Dregisters-aarch64.cc180 const CPURegister& reg8) { in AreAliased() argument
189 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
231 const CPURegister& reg8) { in AreSameSizeAndType() argument
240 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
251 const CPURegister& reg8) { in AreEven() argument
260 even &= !reg8.IsValid() || ((reg8.GetCode() % 2) == 0); in AreEven()
Dregisters-aarch64.h844 const CPURegister& reg8 = NoReg);
857 const CPURegister& reg8 = NoCPUReg);
869 const CPURegister& reg8 = NoReg);
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DRegisterInfos_i386.h162 #define DEFINE_GPR_PSEUDO_8H(reg8, reg32) \ argument
164 #reg8, nullptr, 1, \
168 lldb_##reg8##_i386 }, \
173 #define DEFINE_GPR_PSEUDO_8L(reg8, reg32) \ argument
175 #reg8, nullptr, 1, \
179 lldb_##reg8##_i386 }, \
DRegisterInfos_x86_64.h175 #define DEFINE_GPR_PSEUDO_8H(reg8, reg64) \ argument
177 #reg8, nullptr, 1, \
181 lldb_##reg8##_x86_64 }, \
186 #define DEFINE_GPR_PSEUDO_8L(reg8, reg64) \ argument
188 #reg8, nullptr, 1, \
192 lldb_##reg8##_x86_64 }, \
/external/llvm-project/llvm/test/tools/llvm-objdump/COFF/
Deh_frame.test15 # CHECK: DW_CFA_offset: reg8 -4
/external/llvm/test/DebugInfo/
Ddwarfdump-debug-frame-simple.test10 ; FRAMES-NEXT: DW_CFA_offset: reg8 -4
/external/llvm-project/llvm/test/DebugInfo/
Ddwarfdump-debug-frame-simple.test10 ; FRAMES-NEXT: DW_CFA_offset: {{reg8|EIP}} -4
/external/libvpx/libvpx/third_party/libyuv/source/
Dscale_msa.cc767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
810 reg8 = (v8i16)__msa_dotp_u_h(vec8, const2); in ScaleRowDown34_0_Box_MSA()
822 reg8 = __msa_srar_h(reg8, shft2); in ScaleRowDown34_0_Box_MSA()
828 reg2 = reg2 * 3 + reg8; in ScaleRowDown34_0_Box_MSA()
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
904 reg8 = (v8i16)__msa_dotp_u_h(vec8, const2); in ScaleRowDown34_1_Box_MSA()
916 reg8 = __msa_srar_h(reg8, shft2); in ScaleRowDown34_1_Box_MSA()
922 reg2 += reg8; in ScaleRowDown34_1_Box_MSA()
Drow_msa.cc826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
900 reg8 = reg2 * const_0x4A; in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
916 reg6 -= reg8; in ARGBToUVRow_MSA()
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
2705 reg8 = (v4i32)__msa_ilvr_h((v8i16)zero, (v8i16)vec1); in I444ToARGBRow_MSA()
2711 reg4 -= reg8 * vec_vr; in I444ToARGBRow_MSA()
2713 reg2 -= reg8 * vec_vg; in I444ToARGBRow_MSA()
/external/libyuv/files/source/
Dscale_msa.cc767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
810 reg8 = (v8i16)__msa_dotp_u_h(vec8, const2); in ScaleRowDown34_0_Box_MSA()
822 reg8 = __msa_srar_h(reg8, shft2); in ScaleRowDown34_0_Box_MSA()
828 reg2 = reg2 * 3 + reg8; in ScaleRowDown34_0_Box_MSA()
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
904 reg8 = (v8i16)__msa_dotp_u_h(vec8, const2); in ScaleRowDown34_1_Box_MSA()
916 reg8 = __msa_srar_h(reg8, shft2); in ScaleRowDown34_1_Box_MSA()
922 reg2 += reg8; in ScaleRowDown34_1_Box_MSA()
Drow_msa.cc826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
900 reg8 = reg2 * const_0x4A; in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
916 reg6 -= reg8; in ARGBToUVRow_MSA()
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
2705 reg8 = (v4i32)__msa_ilvr_h((v8i16)zero, (v8i16)vec1); in I444ToARGBRow_MSA()
2711 reg4 -= reg8 * vec_vr; in I444ToARGBRow_MSA()
2713 reg2 -= reg8 * vec_vg; in I444ToARGBRow_MSA()
/external/libaom/libaom/av1/common/arm/
Dconvolve_neon.c1168 int16x4_t reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, in av1_convolve_2d_sr_neon() local
1203 reg8 = vget_low_s16(vreinterpretq_s16_u16(vmovl_u8(t1))); in av1_convolve_2d_sr_neon()
1214 d1 = convolve8_4x4(reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, in av1_convolve_2d_sr_neon()
1217 d2 = convolve8_4x4(reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, in av1_convolve_2d_sr_neon()
1220 d3 = convolve8_4x4(reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, in av1_convolve_2d_sr_neon()
1223 d4 = convolve8_4x4(reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, in av1_convolve_2d_sr_neon()
1226 d5 = convolve8_4x4(reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg12, in av1_convolve_2d_sr_neon()
1229 d6 = convolve8_4x4(reg6, reg7, reg8, reg9, reg10, reg11, reg12, reg13, in av1_convolve_2d_sr_neon()
1232 d7 = convolve8_4x4(reg7, reg8, reg9, reg10, reg11, reg12, reg13, reg14, in av1_convolve_2d_sr_neon()
1252 reg0 = reg8; in av1_convolve_2d_sr_neon()
/external/llvm-project/lldb/tools/debugserver/source/MacOSX/i386/
DDNBArchImplI386.cpp1186 #define DEFINE_GPR_PSEUDO_8H(reg8, reg32) \ argument
1188 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 1, INVALID_NUB_REGNUM, \
1192 #define DEFINE_GPR_PSEUDO_8L(reg8, reg32) \ argument
1194 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 0, INVALID_NUB_REGNUM, \
/external/llvm-project/lldb/tools/debugserver/source/MacOSX/x86_64/
DDNBArchImplX86_64.cpp1622 #define DEFINE_GPR_PSEUDO_8H(reg8, reg64) \ argument
1624 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 1, INVALID_NUB_REGNUM, \
1628 #define DEFINE_GPR_PSEUDO_8L(reg8, reg64) \ argument
1630 e_regSetGPR, gpr_##reg8, #reg8, NULL, Uint, Hex, 1, 0, INVALID_NUB_REGNUM, \
/external/llvm/include/llvm/Support/
DDwarf.def209 HANDLE_DW_OP(0x58, reg8)
/external/llvm/test/CodeGen/AMDGPU/
Dbig_alu.ll5 …eg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg …
13 %tmp6 = extractelement <4 x float> %reg8, i32 0
18 %tmp11 = extractelement <4 x float> %reg8, i32 0
23 %tmp16 = extractelement <4 x float> %reg8, i32 0
28 %tmp21 = extractelement <4 x float> %reg8, i32 0
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dbig_alu.ll5 …eg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg …
13 %tmp6 = extractelement <4 x float> %reg8, i32 0
18 %tmp11 = extractelement <4 x float> %reg8, i32 0
23 %tmp16 = extractelement <4 x float> %reg8, i32 0
28 %tmp21 = extractelement <4 x float> %reg8, i32 0
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/
DDwarf.def563 HANDLE_DW_OP(0x58, reg8, 2, DWARF)
/external/llvm-project/llvm/include/llvm/BinaryFormat/
DDwarf.def581 HANDLE_DW_OP(0x58, reg8, 2, DWARF)
/external/mesa3d/src/freedreno/registers/
Drules-ng-ng.txt147 <reg8>, <reg16>, <reg32> or <reg64> tags. The register of course takes