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Searched refs:reg_1 (Results 1 – 5 of 5) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/x86/
Dvpx_subpixel_8t_intrin_ssse3.c613 __m128i reg_0, reg_1; in vpx_filter_block1d4_v4_ssse3() local
656 reg_1 = _mm_maddubs_epi16(src_reg_m1012_1023_hi, kernel_reg); in vpx_filter_block1d4_v4_ssse3()
658 reg_1 = _mm_hadds_epi16(reg_1, _mm_setzero_si128()); in vpx_filter_block1d4_v4_ssse3()
662 reg_1 = mm_round_epi16_sse2(&reg_1, &reg_32, 6); in vpx_filter_block1d4_v4_ssse3()
666 reg_1 = _mm_packus_epi16(reg_1, reg_1); in vpx_filter_block1d4_v4_ssse3()
670 *((uint32_t *)(dst_ptr + dst_stride)) = _mm_cvtsi128_si32(reg_1); in vpx_filter_block1d4_v4_ssse3()
/external/capstone/arch/M68K/
DM68KDisassembler.c989 int reg_0, reg_1; in build_cas2() local
1005 op0->reg_pair.reg_1 = extension & 7; in build_cas2()
1010 op1->reg_pair.reg_1 = (extension >> 6) & 7; in build_cas2()
1013 reg_1 = (extension >> 12) & 7; in build_cas2()
1018 op2->reg_pair.reg_1 = reg_1 + (BIT_F(extension) ? 8 : 0); in build_cas2()
2246 uint reg_0, reg_1; in d68020_divl() local
2264 reg_1 = (extension >> 12) & 7; in d68020_divl()
2269 op1->reg_pair.reg_1 = reg_1; in d68020_divl()
2271 if ((reg_0 == reg_1) || !BIT_A(extension)) { in d68020_divl()
2273 op1->reg = M68K_REG_D0 + reg_1; in d68020_divl()
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DM68KInstPrinter.c128 s_reg_names[M68K_REG_D0 + op->reg_pair.reg_1]); in registerPair()
/external/gemmlowp/meta/generators/
Dneon_emitter_64.py164 def _MakeCompatibleDown(reg_1, reg_2, reg_3): argument
165 bits = min([reg_1.register_bits, reg_2.register_bits, reg_3.register_bits])
166 return (_Cast(bits, reg_1), _Cast(bits, reg_2), _Cast(bits, reg_3))
169 def _MakeCompatibleUp(reg_1, reg_2, reg_3): argument
170 bits = max([reg_1.register_bits, reg_2.register_bits, reg_3.register_bits])
171 return (_Cast(bits, reg_1), _Cast(bits, reg_2), _Cast(bits, reg_3))
/external/capstone/include/capstone/
Dm68k.h156 m68k_reg reg_1; member