| /external/mesa3d/src/freedreno/ir3/ |
| D | regmask.h | 40 __regmask_get(regmask_t *regmask, bool half, unsigned n) in __regmask_get() argument
42 if (regmask->mergedregs) { in __regmask_get()
48 return BITSET_TEST(regmask->mask, n); in __regmask_get()
51 return BITSET_TEST(regmask->mask, n) || in __regmask_get()
52 BITSET_TEST(regmask->mask, n+1); in __regmask_get()
60 return BITSET_TEST(regmask->mask, n); in __regmask_get()
65 __regmask_set(regmask_t *regmask, bool half, unsigned n) in __regmask_set() argument
67 if (regmask->mergedregs) { in __regmask_set()
73 BITSET_SET(regmask->mask, n); in __regmask_set()
76 BITSET_SET(regmask->mask, n); in __regmask_set()
[all …]
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| D | ir3.h | 1748 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg) in regmask_set() argument
1753 __regmask_set(regmask, half, reg->array.offset + i); in regmask_set()
1757 __regmask_set(regmask, half, n); in regmask_set()
1761 static inline bool regmask_get(regmask_t *regmask, in regmask_get() argument
1767 if (__regmask_get(regmask, half, reg->array.offset + i)) in regmask_get()
1772 if (__regmask_get(regmask, half, n)) in regmask_get()
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| D | disasm-a3xx.c | 170 static void regmask_set(regmask_t *regmask, unsigned num, bool full) in regmask_set() argument
173 __regmask_set(regmask, !full, num); in regmask_set()
176 static void regmask_clear(regmask_t *regmask, unsigned num, bool full) in regmask_clear() argument
179 __regmask_clear(regmask, !full, num); in regmask_clear()
182 static unsigned regmask_get(regmask_t *regmask, unsigned num, bool full) in regmask_get() argument
185 return __regmask_get(regmask, !full, num); in regmask_get()
212 static int print_regs(struct disasm_ctx *ctx, regmask_t *regmask, bool full) in print_regs() argument
220 if (regmask_get(regmask, num, full)) { in print_regs()
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| D | meson.build | 106 'regmask.h',
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | ipra-04.ll | 1 ; Test that the updated regmask on the call to @fun1 preserves %r14 and
4 ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -enable-ipra -print-regmask-num-regs=-1 \
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| /external/llvm-project/llvm/test/DebugInfo/X86/ |
| D | dbg-value-regmask-clobber.ll | 4 ; Values in registers should be clobbered by calls, which use a regmask instead
30 source_filename = "test/DebugInfo/X86/dbg-value-regmask-clobber.ll"
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | ipra-regmask.ll | 2 ; Make sure the expected regmask is generated for sub/superregisters.
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| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | livephysregs-regmask-clobber.mir | 4 # but both are clobbered by the regmask. Only V0 is re-defined before the
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 96 // Just to get the regmask, not for calling convention purposes.
101 // Just to get the regmask, not for calling convention purposes.
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| /external/llvm/test/CodeGen/ARM/ |
| D | ifcvt-regmask-noreturn.ll | 11 ; Prior to this change, the stack_chk call (which does not return) would clobber R0 in its regmask,
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | ifcvt-regmask-noreturn.ll | 11 ; Prior to this change, the stack_chk call (which does not return) would clobber R0 in its regmask,
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallingConv.td | 182 // Just to get the regmask, not for calling convention purposes.
187 // Just to get the regmask, not for calling convention purposes.
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | regcoal-physreg.mir | 65 ; clobbered by the regmask on a call.
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| D | aarch64-a57-fp-load-balancing.ll | 260 ; Test that regmask clobbering stops a chain sequence.
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| /external/llvm/test/DebugInfo/X86/ |
| D | dbg-value-regmask-clobber.ll | 4 ; Values in registers should be clobbered by calls, which use a regmask instead
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| /external/llvm/test/CodeGen/X86/ |
| D | x86-shrink-wrapping.ll | 735 ; CHECK-LABEL: regmask:
772 define i32 @regmask(i32 %a, i32 %b, i32* %addr) {
777 ; Clobber a CSR so that we check something on the regmask
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | x86-shrink-wrapping.ll | 1109 define i32 @regmask(i32 %a, i32 %b, i32* %addr) {
1110 ; ENABLE-LABEL: regmask:
1131 ; DISABLE-LABEL: regmask:
1156 ; Clobber a CSR so that we check something on the regmask
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| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-a57-fp-load-balancing.ll | 260 ; Test that regmask clobbering stops a chain sequence.
|
| /external/llvm-project/llvm/docs/ |
| D | MIRLangRef.rst | 204 CALL64pcrel32 @foo <regmask...>
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| /external/mesa3d/docs/relnotes/ |
| D | 20.1.0.rst | 3664 - freedreno/ir3: rewrite regmask to better support a6xx+
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| D | 19.1.0.rst | 4113 - freedreno/ir3: fix regmask for merged regs
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| D | 20.2.0.rst | 4183 - freedreno/ir3: split out regmask
|