| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 384 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, in regmaskSubsetEqual() function in TargetRegisterInfo
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 463 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, in regmaskSubsetEqual() function in TargetRegisterInfo
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 480 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 480 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, in regmaskSubsetEqual() function in TargetRegisterInfo
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 460 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 473 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 558 return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved); in doCallerAndCalleePassArgsTheSameWay()
|
| D | AArch64ISelLowering.cpp | 3844 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 583 return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved); in doCallerAndCalleePassArgsTheSameWay()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2079 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2776 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2841 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2641 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2864 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2146 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in IsEligibleForTailCallOptimization()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5001 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in isEligibleForTailCallOptimization()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2647 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in IsEligibleForTailCallOptimization()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2837 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in IsEligibleForTailCallOptimization()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3679 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in IsEligibleForTailCallOptimization()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4565 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in IsEligibleForTailCallOptimization()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4662 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) in IsEligibleForTailCallOptimization()
|