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Searched refs:res10 (Results 1 – 25 of 30) sorted by relevance

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/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dfp-arith.ll22 %res10 = fadd <16 x double> undef, undef
38 ; CHECK: Cost Model: Found an estimated cost of 8 for instruction: %res10 = fadd <16 x double> un…
54 %res10 = fsub <16 x double> undef, undef
70 ; CHECK: Cost Model: Found an estimated cost of 8 for instruction: %res10 = fsub <16 x double> un…
86 %res10 = fmul <16 x double> undef, undef
102 ; CHECK: Cost Model: Found an estimated cost of 8 for instruction: %res10 = fmul <16 x double> un…
118 %res10 = fdiv <16 x double> undef, undef
134 ; CHECK: Cost Model: Found an estimated cost of 8 for instruction: %res10 = fdiv <16 x double> un…
Dlogical.ll14 %res10 = and <4 x i32> undef, undef
35 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = and <4 x i32> undef, …
60 %res10 = ashr <4 x i32> undef, undef
81 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = ashr <4 x i32> undef,…
106 %res10 = lshr <4 x i32> undef, undef
127 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = lshr <4 x i32> undef,…
152 %res10 = or <4 x i32> undef, undef
173 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = or <4 x i32> undef, u…
198 %res10 = shl <4 x i32> undef, undef
219 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = shl <4 x i32> undef, …
[all …]
Dint-arith.ll17 %res10 = add <4 x i32> undef, undef
38 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = add <4 x i32> undef, …
63 %res10 = sub <4 x i32> undef, undef
84 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = sub <4 x i32> undef, …
109 %res10 = mul <4 x i32> undef, undef
130 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = mul <4 x i32> undef, …
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
456 ILVR_B2_SH(zero, dst10, zero, dst11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
457 ADD2(res10, out10, res11, out11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
458 CLIP_SH2_0_255(res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
459 PCKEV_B2_SH(res10, res10, res11, res11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
460 ST8x1_UB(res10, dst + 6 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm-project/llvm/test/Bitcode/
DmiscInstructions.3.2.ll102 ; CHECK-NEXT: %res10 = icmp sle i32 %x1, %x2
103 %res10 = icmp sle i32 %x1, %x2
144 ; CHECK-NEXT: %res10 = fcmp ole float %x1, %x2
145 %res10 = fcmp ole float %x1, %x2
DmemInstructions.3.2.ll57 ; CHECK-NEXT: %res10 = load volatile i8, i8* %ptr1, align 1, !invariant.load !1
58 %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
113 ; CHECK-NEXT: %res10 = load atomic i8, i8* %ptr1 syncscope("singlethread") monotonic, align 1
114 %res10 = load atomic i8, i8* %ptr1 syncscope("singlethread") monotonic, align 1
266 ; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
267 %res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll102 ; CHECK-NEXT: %res10 = icmp sle i32 %x1, %x2
103 %res10 = icmp sle i32 %x1, %x2
144 ; CHECK-NEXT: %res10 = fcmp ole float %x1, %x2
145 %res10 = fcmp ole float %x1, %x2
DmemInstructions.3.2.ll57 ; CHECK-NEXT: %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
58 %res10 = load volatile i8, i8* %ptr1, !invariant.load !1
113 ; CHECK-NEXT: %res10 = load atomic i8, i8* %ptr1 singlethread monotonic, align 1
114 %res10 = load atomic i8, i8* %ptr1 singlethread monotonic, align 1
266 ; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
267 %res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
/external/clang/test/SemaCXX/
Daltivec.cpp29 int res10[vec_step(vi) == 4 ? 1 : -1]; in test_vec_step() local
/external/llvm-project/clang/test/SemaCXX/
Daltivec.cpp29 int res10[vec_step(vi) == 4 ? 1 : -1]; in test_vec_step() local
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll165 %res10 = zext <16 x i1> %res10_i1 to <16 x i8>
166 ret <16 x i8> %res10
321 %res10 = insertelement <16 x i8> %vec, i8 %elt, i32 10
322 ret <16 x i8> %res10
509 %res10 = zext i1 %res10_i1 to i64
510 ret i64 %res10
685 %res10 = zext i8 %res10_i8 to i64
686 ret i64 %res10
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll41 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
43 ret <4 x i32> %res10
/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll41 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
43 ret <4 x i32> %res10
/external/llvm-project/clang/test/SemaOpenCL/
Dvec_step.cl25 int res10[vec_step(int8) == 8 ? 1 : -1];
/external/clang/test/SemaOpenCL/
Dvec_step.cl25 int res10[vec_step(int8) == 8 ? 1 : -1];
/external/libaom/libaom/av1/common/arm/
Dwiener_convolve_neon.c83 uint16x8_t res5, res6, res7, res8, res9, res10, res11; in av1_wiener_convolve_add_src_neon() local
164 res10 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
174 transpose_u16_8x8(&res4, &res5, &res6, &res7, &res8, &res9, &res10, in av1_wiener_convolve_add_src_neon()
177 res10, res11); in av1_wiener_convolve_add_src_neon()
Djnt_convolve_neon.c1139 uint16x8_t res9, res10, res11; in av1_dist_wtd_convolve_x_neon() local
1226 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_x_neon()
1229 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res0), in av1_dist_wtd_convolve_x_neon()
1239 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_x_neon()
1242 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res4), in av1_dist_wtd_convolve_x_neon()
1574 uint16x8_t res10, res11, res9; in av1_dist_wtd_convolve_y_neon() local
1651 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_y_neon()
1654 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res0), in av1_dist_wtd_convolve_y_neon()
1664 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_y_neon()
1667 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res4), in av1_dist_wtd_convolve_y_neon()
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-sadd-08.ll252 %res10 = or i1 %res9, %obit10
256 %res11 = or i1 %res10, %obit11
384 %res10 = or i1 %res9, %obit10
388 %res11 = or i1 %res10, %obit11
Dint-sadd-09.ll252 %res10 = or i1 %res9, %obit10
256 %res11 = or i1 %res10, %obit11
384 %res10 = or i1 %res9, %obit10
388 %res11 = or i1 %res10, %obit11
Dint-ssub-09.ll252 %res10 = or i1 %res9, %obit10
256 %res11 = or i1 %res10, %obit11
384 %res10 = or i1 %res9, %obit10
388 %res11 = or i1 %res10, %obit11
Dint-usub-10.ll252 %res10 = or i1 %res9, %obit10
256 %res11 = or i1 %res10, %obit11
384 %res10 = or i1 %res9, %obit10
388 %res11 = or i1 %res10, %obit11
Dint-ssub-08.ll252 %res10 = or i1 %res9, %obit10
256 %res11 = or i1 %res10, %obit11
384 %res10 = or i1 %res9, %obit10
388 %res11 = or i1 %res10, %obit11
Dint-uadd-10.ll242 %res10 = or i1 %res9, %obit10
246 %res11 = or i1 %res10, %obit11
374 %res10 = or i1 %res9, %obit10
378 %res11 = or i1 %res10, %obit11
Dint-usub-11.ll253 %res10 = or i1 %res9, %obit10
257 %res11 = or i1 %res10, %obit11
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h621 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
850 res10 = mult_round_shift(&t2, &t3, &k__cospi_p12_p20, in FDCT16x16_2D()
856 check_epi16_overflow_x4(&res02, &res14, &res10, &res06); in FDCT16x16_2D()
1001 transpose_and_output8x8(&res08, &res09, &res10, &res11, &res12, &res13, in FDCT16x16_2D()

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