Home
last modified time | relevance | path

Searched refs:res5 (Results 1 – 25 of 87) sorted by relevance

1234

/external/llvm-project/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll22 ; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
23 %res5 = fadd x86_fp80 %x5, %x5
45 ; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
46 %res5 = fadd <16 x float> %x5, %x5
65 ; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
66 %res5 = fadd <16 x double> %x5, %x5
85 ; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
86 %res5 = fadd <16 x half> %x5, %x5
DbinaryIntInstructions.3.2.ll22 ; CHECK-NEXT: %res5 = add i64 %x5, %x5
23 %res5 = add i64 %x5, %x5
51 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
52 %res5 = add nuw nsw <16 x i8> %x5, %x5
71 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
72 %res5 = add nuw nsw <16 x i16> %x5, %x5
91 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
92 %res5 = add nuw nsw <16 x i32> %x5, %x5
111 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
112 %res5 = add nuw nsw <16 x i64> %x5, %x5
DmiscInstructions.3.2.ll87 ; CHECK-NEXT: %res5 = icmp ult i32 %x1, %x2
88 %res5 = icmp ult i32 %x1, %x2
129 ; CHECK-NEXT: %res5 = fcmp ult float %x1, %x2
130 %res5 = fcmp ult float %x1, %x2
DmemInstructions.3.2.ll42 ; CHECK-NEXT: %res5 = load i8, i8* %ptr1, align 1, !nontemporal !0
43 %res5 = load i8, i8* %ptr1, !nontemporal !0
98 ; CHECK-NEXT: %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
99 %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
245 ; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
246 %res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
/external/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll22 ; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
23 %res5 = fadd x86_fp80 %x5, %x5
45 ; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
46 %res5 = fadd <16 x float> %x5, %x5
65 ; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
66 %res5 = fadd <16 x double> %x5, %x5
85 ; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
86 %res5 = fadd <16 x half> %x5, %x5
DbinaryIntInstructions.3.2.ll22 ; CHECK-NEXT: %res5 = add i64 %x5, %x5
23 %res5 = add i64 %x5, %x5
51 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
52 %res5 = add nuw nsw <16 x i8> %x5, %x5
71 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
72 %res5 = add nuw nsw <16 x i16> %x5, %x5
91 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
92 %res5 = add nuw nsw <16 x i32> %x5, %x5
111 ; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
112 %res5 = add nuw nsw <16 x i64> %x5, %x5
DmiscInstructions.3.2.ll87 ; CHECK-NEXT: %res5 = icmp ult i32 %x1, %x2
88 %res5 = icmp ult i32 %x1, %x2
129 ; CHECK-NEXT: %res5 = fcmp ult float %x1, %x2
130 %res5 = fcmp ult float %x1, %x2
DmemInstructions.3.2.ll42 ; CHECK-NEXT: %res5 = load i8, i8* %ptr1, !nontemporal !0
43 %res5 = load i8, i8* %ptr1, !nontemporal !0
98 ; CHECK-NEXT: %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
99 %res5 = load atomic volatile i8, i8* %ptr1 unordered, align 1
245 ; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
246 %res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
/external/icu/icu4c/source/test/intltest/
Dnmfmapts.cpp124 UnicodeString res1, res2, res3, res4, res5, res6; in testAPI() local
140 res5 = cur_fr->format(fD, res5, pos3, status); in testAPI()
144 logln((UnicodeString) "" + (int32_t) fD.getDouble() + " formatted to " + res5); in testAPI()
332 UnicodeString res0, res1, res2, res3, res4, res5; in testRegistration() local
342 f5->format(n, res5); in testRegistration()
353 logln((UnicodeString)"f5 unreg cur: " + res5); in testRegistration()
371 if (res5 != res2) { in testRegistration()
/external/llvm/test/CodeGen/X86/
Davx512ifmavl-intrinsics.ll27 %res5 = add <2 x i64> %res3, %res2
28 %res6 = add <2 x i64> %res5, %res4
55 %res5 = add <4 x i64> %res3, %res2
56 %res6 = add <4 x i64> %res5, %res4
83 %res5 = add <2 x i64> %res3, %res2
84 %res6 = add <2 x i64> %res5, %res4
111 %res5 = add <4 x i64> %res3, %res2
112 %res6 = add <4 x i64> %res5, %res4
139 %res5 = add <2 x i64> %res3, %res2
140 %res6 = add <2 x i64> %res5, %res4
[all …]
Davx512ifma-intrinsics.ll24 %res5 = add <8 x i64> %res3, %res2
25 %res6 = add <8 x i64> %res5, %res4
50 %res5 = add <8 x i64> %res3, %res2
51 %res6 = add <8 x i64> %res5, %res4
76 %res5 = add <8 x i64> %res3, %res2
77 %res6 = add <8 x i64> %res5, %res4
102 %res5 = add <8 x i64> %res3, %res2
103 %res6 = add <8 x i64> %res5, %res4
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dfp-arith.ll17 %res5 = fadd <4 x float> undef, undef
30 ; CHECK-Z13: Cost Model: Found an estimated cost of 8 for instruction: %res5 = fadd <4 x float> u…
31 ; CHECK-Z14: Cost Model: Found an estimated cost of 1 for instruction: %res5 = fadd <4 x float> u…
49 %res5 = fsub <4 x float> undef, undef
62 ; CHECK-Z13: Cost Model: Found an estimated cost of 8 for instruction: %res5 = fsub <4 x float> u…
63 ; CHECK-Z14: Cost Model: Found an estimated cost of 1 for instruction: %res5 = fsub <4 x float> u…
81 %res5 = fmul <4 x float> undef, undef
94 ; CHECK-Z13: Cost Model: Found an estimated cost of 8 for instruction: %res5 = fmul <4 x float> u…
95 ; CHECK-Z14: Cost Model: Found an estimated cost of 1 for instruction: %res5 = fmul <4 x float> u…
113 %res5 = fdiv <4 x float> undef, undef
[all …]
Dlogical.ll9 %res5 = and <2 x i16> undef, undef
30 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = and <2 x i16> undef, u…
55 %res5 = ashr <2 x i16> undef, undef
76 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = ashr <2 x i16> undef, …
101 %res5 = lshr <2 x i16> undef, undef
122 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = lshr <2 x i16> undef, …
147 %res5 = or <2 x i16> undef, undef
168 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = or <2 x i16> undef, un…
193 %res5 = shl <2 x i16> undef, undef
214 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = shl <2 x i16> undef, u…
[all …]
Dint-arith.ll12 %res5 = add <2 x i16> undef, undef
33 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = add <2 x i16> undef, u…
58 %res5 = sub <2 x i16> undef, undef
79 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = sub <2 x i16> undef, u…
104 %res5 = mul <2 x i16> undef, undef
125 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = mul <2 x i16> undef, u…
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c267 v8i16 vec, res0, res1, res2, res3, res4, res5, res6, res7; in vpx_idct16x16_1_add_msa() local
279 UNPCK_UB_SH(dst1, res1, res5); in vpx_idct16x16_1_add_msa()
283 ADD4(res4, vec, res5, vec, res6, vec, res7, vec, res4, res5, res6, res7); in vpx_idct16x16_1_add_msa()
285 CLIP_SH4_0_255(res4, res5, res6, res7); in vpx_idct16x16_1_add_msa()
286 PCKEV_B4_UB(res4, res0, res5, res1, res6, res2, res7, res3, tmp0, tmp1, in vpx_idct16x16_1_add_msa()
331 v8i16 res0, res1, res2, res3, res4, res5, res6, res7; in vpx_iadst16_1d_columns_addblk_msa() local
420 ILVR_B2_SH(zero, dst4, zero, dst5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
421 ADD2(res4, out4, res5, out5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
422 CLIP_SH2_0_255(res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
423 PCKEV_B2_SH(res4, res4, res5, res5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
[all …]
Dvpx_convolve8_avg_horiz_msa.c497 v8u16 res0, res1, res2, res3, res4, res5, res6, res7, filt; in common_hz_2t_and_aver_dst_16w_msa() local
515 DOTP_UB4_UH(vec4, vec5, vec6, vec7, filt0, filt0, filt0, filt0, res4, res5, in common_hz_2t_and_aver_dst_16w_msa()
518 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_16w_msa()
524 PCKEV_AVG_ST_UB(res5, res4, dst2, dst); in common_hz_2t_and_aver_dst_16w_msa()
540 DOTP_UB4_UH(vec4, vec5, vec6, vec7, filt0, filt0, filt0, filt0, res4, res5, in common_hz_2t_and_aver_dst_16w_msa()
543 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_16w_msa()
549 PCKEV_AVG_ST_UB(res5, res4, dst2, dst); in common_hz_2t_and_aver_dst_16w_msa()
564 v8u16 res0, res1, res2, res3, res4, res5, res6, res7, filt; in common_hz_2t_and_aver_dst_32w_msa() local
590 DOTP_UB4_UH(vec4, vec5, vec6, vec7, filt0, filt0, filt0, filt0, res4, res5, in common_hz_2t_and_aver_dst_32w_msa()
593 SRARI_H4_UH(res4, res5, res6, res7, FILTER_BITS); in common_hz_2t_and_aver_dst_32w_msa()
[all …]
/external/libaom/libaom/av1/common/arm/
Djnt_convolve_neon.c443 int16x8_t res1, res2, res3, res4, res5, res6, res7; in dist_wtd_convolve_2d_horiz_neon() local
496 res5 = convolve8_8x8_s16(s5, s6, s7, s8, s9, s10, s11, s12, in dist_wtd_convolve_2d_horiz_neon()
503 transpose_s16_8x8(&res0, &res1, &res2, &res3, &res4, &res5, &res6, in dist_wtd_convolve_2d_horiz_neon()
506 store_s16_8x8(d_tmp, dst_stride, res0, res1, res2, res3, res4, res5, in dist_wtd_convolve_2d_horiz_neon()
594 uint16x4_t res5, res6, res7, d1, d2, d3; in dist_wtd_convolve_2d_vert_neon() local
647 load_u16_4x4(d, dst_stride, &res4, &res5, &res6, &res7); in dist_wtd_convolve_2d_vert_neon()
650 compute_avg_4x4(res4, res5, res6, res7, d0, d1, d2, d3, fwd_offset, in dist_wtd_convolve_2d_vert_neon()
762 uint16x4_t tmp4, tmp5, tmp6, tmp7, res4, res5, res6, res7; in av1_dist_wtd_convolve_2d_copy_neon() local
841 res5 = vadd_u16(vshl_u16(vget_low_u16(vmovl_u8(res1_8)), dup_bits16x4), in av1_dist_wtd_convolve_2d_copy_neon()
850 compute_avg_4x4(tmp4, tmp5, tmp6, tmp7, res4, res5, res6, res7, in av1_dist_wtd_convolve_2d_copy_neon()
[all …]
Dwiener_convolve_neon.c83 uint16x8_t res5, res6, res7, res8, res9, res10, res11; in av1_wiener_convolve_add_src_neon() local
129 res5 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
174 transpose_u16_8x8(&res4, &res5, &res6, &res7, &res8, &res9, &res10, in av1_wiener_convolve_add_src_neon()
176 store_u16_8x8(d_tmp, MAX_SB_SIZE, res4, res5, res6, res7, res8, res9, in av1_wiener_convolve_add_src_neon()
248 uint16x4_t res0, res1, res2, res3, res4, res5, res6, res7; in av1_wiener_convolve_add_src_neon() local
313 res5 = in av1_wiener_convolve_add_src_neon()
323 transpose_u16_4x8(&res0, &res1, &res2, &res3, &res4, &res5, &res6, in av1_wiener_convolve_add_src_neon()
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/format/
DIntlTestNumberFormatAPI.java91 StringBuffer res5 = new StringBuffer(); in TestAPI() local
110 res5 = cur_fr.format(d, res5, pos3); in TestAPI()
111 logln("" + d + " formatted to " + res5); in TestAPI()
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/format/
DIntlTestNumberFormatAPI.java94 StringBuffer res5 = new StringBuffer(); in TestAPI() local
113 res5 = cur_fr.format(d, res5, pos3); in TestAPI()
114 logln("" + d + " formatted to " + res5); in TestAPI()
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll88 %res5 = zext <8 x i1> %res5_i1 to <8 x i16>
89 ret <8 x i16> %res5
145 %res5 = zext <16 x i1> %res5_i1 to <16 x i8>
146 ret <16 x i8> %res5
251 %res5 = insertelement <8 x i16> %vec, i16 %elt, i32 5
252 ret <8 x i16> %res5
306 %res5 = insertelement <16 x i8> %vec, i8 %elt, i32 5
307 ret <16 x i8> %res5
433 %res5 = zext i1 %res5_i1 to i64
434 ret i64 %res5
[all …]
/external/libyuv/files/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
229 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeUVWx16_MSA()
/external/libvpx/libvpx/third_party/libyuv/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
229 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeUVWx16_MSA()
/external/libaom/libaom/aom_dsp/x86/
Dfwd_txfm_impl_sse2.h276 __m128i res0, res1, res2, res3, res4, res5, res6, res7; in FDCT8x8_2D() local
430 res5 = _mm_packs_epi32(w4, w5); in FDCT8x8_2D()
433 overflow = check_epi16_overflow_x4(&res1, &res7, &res5, &res3); in FDCT8x8_2D()
456 const __m128i tr0_4 = _mm_unpacklo_epi16(res4, res5); in FDCT8x8_2D()
458 const __m128i tr0_6 = _mm_unpackhi_epi16(res4, res5); in FDCT8x8_2D()
/external/clang/test/SemaCXX/
Daltivec.cpp24 int res5[vec_step(vbs) == 8 ? 1 : -1]; in test_vec_step() local

1234