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Searched refs:res8 (Results 1 – 25 of 57) sorted by relevance

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/external/libyuv/files/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
134 ILVRL_D(res0, res8, res1, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
139 ILVRL_D(res2, res8, res3, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
142 res8 = (v16u8)__msa_ilvr_w((v4i32)reg6, (v4i32)reg2); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
149 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
[all …]
/external/libvpx/libvpx/third_party/libyuv/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
134 ILVRL_D(res0, res8, res1, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
139 ILVRL_D(res2, res8, res3, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
142 res8 = (v16u8)__msa_ilvr_w((v4i32)reg6, (v4i32)reg2); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
149 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
[all …]
/external/tensorflow/tensorflow/lite/kernels/
Dcpu_backend_gemm_custom_gemv.h241 uint8x8_t res8 = vqmovun_s16(vcombine_s16(res16, res16)); in ClampAndStore() local
243 res8 = vmax_u8(res8, vdup_n_u8(clamp_min)); in ClampAndStore()
244 res8 = vmin_u8(res8, vdup_n_u8(clamp_max)); in ClampAndStore()
246 vst1_lane_u8(dst + 0, res8, 0); in ClampAndStore()
247 vst1_lane_u8(dst + 1, res8, 1); in ClampAndStore()
248 vst1_lane_u8(dst + 2, res8, 2); in ClampAndStore()
249 vst1_lane_u8(dst + 3, res8, 3); in ClampAndStore()
257 int8x8_t res8 = vqmovn_s16(vcombine_s16(res16, res16)); in ClampAndStore() local
259 res8 = vmax_s8(res8, vdup_n_s8(clamp_min)); in ClampAndStore()
260 res8 = vmin_s8(res8, vdup_n_s8(clamp_max)); in ClampAndStore()
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dfp-arith.ll20 %res8 = fadd <8 x double> undef, undef
35 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res8 = fadd <8 x double> unde…
52 %res8 = fsub <8 x double> undef, undef
67 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res8 = fsub <8 x double> unde…
84 %res8 = fmul <8 x double> undef, undef
99 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res8 = fmul <8 x double> unde…
116 %res8 = fdiv <8 x double> undef, undef
131 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res8 = fdiv <8 x double> unde…
Dlogical.ll12 %res8 = and <4 x i8> undef, undef
33 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = and <4 x i8> undef, un…
58 %res8 = ashr <4 x i8> undef, undef
79 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = ashr <4 x i8> undef, u…
104 %res8 = lshr <4 x i8> undef, undef
125 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = lshr <4 x i8> undef, u…
150 %res8 = or <4 x i8> undef, undef
171 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = or <4 x i8> undef, und…
196 %res8 = shl <4 x i8> undef, undef
217 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = shl <4 x i8> undef, un…
[all …]
Dint-arith.ll15 %res8 = add <4 x i8> undef, undef
36 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = add <4 x i8> undef, un…
61 %res8 = sub <4 x i8> undef, undef
82 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = sub <4 x i8> undef, un…
107 %res8 = mul <4 x i8> undef, undef
128 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = mul <4 x i8> undef, un…
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
405 ILVR_B2_SH(zero, dst8, zero, dst9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
406 ADD2(res8, out8, res9, out9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
407 CLIP_SH2_0_255(res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
408 PCKEV_B2_SH(res8, res8, res9, res9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
409 ST8x1_UB(res8, dst + dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_query_hw.c274 uint8_t *res8 = (uint8_t *)result; in nv50_hw_get_query_result() local
300 res8[0] = true; in nv50_hw_get_query_result()
307 res8[0] = hq->data[1] != hq->data[5]; in nv50_hw_get_query_result()
326 res8[8] = false; in nv50_hw_get_query_result()
/external/llvm-project/llvm/test/Bitcode/
DmiscInstructions.3.2.ll96 ; CHECK-NEXT: %res8 = icmp sge i32 %x1, %x2
97 %res8 = icmp sge i32 %x1, %x2
138 ; CHECK-NEXT: %res8 = fcmp oge float %x1, %x2
139 %res8 = fcmp oge float %x1, %x2
DmemInstructions.3.2.ll51 ; CHECK-NEXT: %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
52 %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
107 ; CHECK-NEXT: %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
108 %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
257 ; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
258 %res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new syncscope("singlethread") acquire acquire
DbinaryIntInstructions.3.2.ll31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll96 ; CHECK-NEXT: %res8 = icmp sge i32 %x1, %x2
97 %res8 = icmp sge i32 %x1, %x2
138 ; CHECK-NEXT: %res8 = fcmp oge float %x1, %x2
139 %res8 = fcmp oge float %x1, %x2
DmemInstructions.3.2.ll51 ; CHECK-NEXT: %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
52 %res8 = load volatile i8, i8* %ptr1, align 1, !nontemporal !0
107 ; CHECK-NEXT: %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
108 %res8 = load atomic volatile i8, i8* %ptr1 seq_cst, align 1
257 ; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
258 %res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_query_hw.c314 uint8_t *res8 = (uint8_t*)result; in nvc0_hw_get_query_result() local
341 res8[0] = true; in nvc0_hw_get_query_result()
348 res8[0] = hq->data[1] != hq->data[5]; in nvc0_hw_get_query_result()
360 res8[0] = data64[0] != data64[2]; in nvc0_hw_get_query_result()
367 res8[8] = false; in nvc0_hw_get_query_result()
/external/libaom/libaom/av1/common/arm/
Djnt_convolve_neon.c1125 uint16x8_t res8; in av1_dist_wtd_convolve_x_neon() local
1226 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_x_neon()
1229 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res0), in av1_dist_wtd_convolve_x_neon()
1239 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_x_neon()
1242 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res4), in av1_dist_wtd_convolve_x_neon()
1314 res8 = vld1q_u16(d_tmp); in av1_dist_wtd_convolve_x_neon()
1317 compute_avg_8x1(res8, vreinterpretq_u16_s16(res0), fwd_offset, in av1_dist_wtd_convolve_x_neon()
1565 uint16x8_t res8; in av1_dist_wtd_convolve_y_neon() local
1651 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_y_neon()
1654 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res0), in av1_dist_wtd_convolve_y_neon()
[all …]
Dwiener_convolve_neon.c83 uint16x8_t res5, res6, res7, res8, res9, res10, res11; in av1_wiener_convolve_add_src_neon() local
150 res8 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
174 transpose_u16_8x8(&res4, &res5, &res6, &res7, &res8, &res9, &res10, in av1_wiener_convolve_add_src_neon()
176 store_u16_8x8(d_tmp, MAX_SB_SIZE, res4, res5, res6, res7, res8, res9, in av1_wiener_convolve_add_src_neon()
/external/clang/test/SemaCXX/
Daltivec.cpp27 int res8[vec_step(vp) == 8 ? 1 : -1]; in test_vec_step() local
/external/llvm-project/clang/test/SemaCXX/
Daltivec.cpp27 int res8[vec_step(vp) == 8 ? 1 : -1]; in test_vec_step() local
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll157 %res8 = zext <16 x i1> %res8_i1 to <16 x i8>
158 ret <16 x i8> %res8
315 %res8 = insertelement <16 x i8> %vec, i8 %elt, i32 8
316 ret <16 x i8> %res8
501 %res8 = zext i1 %res8_i1 to i64
502 ret i64 %res8
677 %res8 = zext i8 %res8_i8 to i64
678 ret i64 %res8
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll37 %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
39 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll37 %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1)
39 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
/external/llvm-project/clang/test/SemaOpenCL/
Dvec_step.cl23 int res8[vec_step(int3) == 4 ? 1 : -1];
/external/clang/test/SemaOpenCL/
Dvec_step.cl23 int res8[vec_step(int3) == 4 ? 1 : -1];
/external/ethtool/
Dfec_8xx.c40 uint32_t res8[14]; /* reserved */ member
/external/llvm-project/polly/test/Isl/CodeGen/
Dinvariant_load_base_pointer_conditional_2.ll65 ; IRA-NEXT: %.res8 = extractvalue { i64, i1 } %21, 0
66 ; IRA-NEXT: %22 = icmp sge i64 %.res8, -2147483648

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