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Searched refs:res9 (Results 1 – 25 of 48) sorted by relevance

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/external/libyuv/files/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
134 ILVRL_D(res0, res8, res1, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
139 ILVRL_D(res2, res8, res3, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
143 res9 = (v16u8)__msa_ilvl_w((v4i32)reg6, (v4i32)reg2); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
149 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
[all …]
/external/libvpx/libvpx/third_party/libyuv/source/
Drotate_msa.cc86 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeWx16_MSA() local
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
134 ILVRL_D(res0, res8, res1, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
139 ILVRL_D(res2, res8, res3, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
143 res9 = (v16u8)__msa_ilvl_w((v4i32)reg6, (v4i32)reg2); in TransposeWx16_MSA()
144 ILVRL_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3); in TransposeWx16_MSA()
149 ILVRL_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3); in TransposeWx16_MSA()
167 v16u8 res0, res1, res2, res3, res4, res5, res6, res7, res8, res9; in TransposeUVWx16_MSA() local
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dfp-arith.ll21 %res9 = fadd <16 x float> undef, undef
36 ; CHECK-Z13: Cost Model: Found an estimated cost of 32 for instruction: %res9 = fadd <16 x float>…
37 ; CHECK-Z14: Cost Model: Found an estimated cost of 4 for instruction: %res9 = fadd <16 x float> …
53 %res9 = fsub <16 x float> undef, undef
68 ; CHECK-Z13: Cost Model: Found an estimated cost of 32 for instruction: %res9 = fsub <16 x float>…
69 ; CHECK-Z14: Cost Model: Found an estimated cost of 4 for instruction: %res9 = fsub <16 x float> …
85 %res9 = fmul <16 x float> undef, undef
100 ; CHECK-Z13: Cost Model: Found an estimated cost of 32 for instruction: %res9 = fmul <16 x float>…
101 ; CHECK-Z14: Cost Model: Found an estimated cost of 4 for instruction: %res9 = fmul <16 x float> …
117 %res9 = fdiv <16 x float> undef, undef
[all …]
Dlogical.ll13 %res9 = and <4 x i16> undef, undef
34 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = and <4 x i16> undef, u…
59 %res9 = ashr <4 x i16> undef, undef
80 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = ashr <4 x i16> undef, …
105 %res9 = lshr <4 x i16> undef, undef
126 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = lshr <4 x i16> undef, …
151 %res9 = or <4 x i16> undef, undef
172 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = or <4 x i16> undef, un…
197 %res9 = shl <4 x i16> undef, undef
218 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = shl <4 x i16> undef, u…
[all …]
Dint-arith.ll16 %res9 = add <4 x i16> undef, undef
37 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = add <4 x i16> undef, u…
62 %res9 = sub <4 x i16> undef, undef
83 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = sub <4 x i16> undef, u…
108 %res9 = mul <4 x i16> undef, undef
129 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = mul <4 x i16> undef, u…
/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
405 ILVR_B2_SH(zero, dst8, zero, dst9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
406 ADD2(res8, out8, res9, out9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
407 CLIP_SH2_0_255(res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
408 PCKEV_B2_SH(res8, res8, res9, res9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
410 ST8x1_UB(res9, dst + 14 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm-project/llvm/test/Bitcode/
DmiscInstructions.3.2.ll99 ; CHECK-NEXT: %res9 = icmp slt i32 %x1, %x2
100 %res9 = icmp slt i32 %x1, %x2
141 ; CHECK-NEXT: %res9 = fcmp olt float %x1, %x2
142 %res9 = fcmp olt float %x1, %x2
DmemInstructions.3.2.ll54 ; CHECK-NEXT: %res9 = load i8, i8* %ptr1, align 1, !invariant.load !1
55 %res9 = load i8, i8* %ptr1, !invariant.load !1
110 ; CHECK-NEXT: %res9 = load atomic i8, i8* %ptr1 syncscope("singlethread") unordered, align 1
111 %res9 = load atomic i8, i8* %ptr1 syncscope("singlethread") unordered, align 1
262 ; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
263 %res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
/external/llvm/test/Bitcode/
DmiscInstructions.3.2.ll99 ; CHECK-NEXT: %res9 = icmp slt i32 %x1, %x2
100 %res9 = icmp slt i32 %x1, %x2
141 ; CHECK-NEXT: %res9 = fcmp olt float %x1, %x2
142 %res9 = fcmp olt float %x1, %x2
DmemInstructions.3.2.ll54 ; CHECK-NEXT: %res9 = load i8, i8* %ptr1, !invariant.load !1
55 %res9 = load i8, i8* %ptr1, !invariant.load !1
110 ; CHECK-NEXT: %res9 = load atomic i8, i8* %ptr1 singlethread unordered, align 1
111 %res9 = load atomic i8, i8* %ptr1 singlethread unordered, align 1
262 ; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
263 %res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
/external/clang/test/SemaCXX/
Daltivec.cpp28 int res9[vec_step(vbi) == 4 ? 1 : -1]; in test_vec_step() local
/external/llvm-project/clang/test/SemaCXX/
Daltivec.cpp28 int res9[vec_step(vbi) == 4 ? 1 : -1]; in test_vec_step() local
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll161 %res9 = zext <16 x i1> %res9_i1 to <16 x i8>
162 ret <16 x i8> %res9
318 %res9 = insertelement <16 x i8> %vec, i8 %elt, i32 9
319 ret <16 x i8> %res9
505 %res9 = zext i1 %res9_i1 to i64
506 ret i64 %res9
681 %res9 = zext i8 %res9_i8 to i64
682 ret i64 %res9
/external/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll39 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
41 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
/external/llvm-project/llvm/test/CodeGen/ARM/
Dintrinsics-crypto.ll39 %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1)
41 %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3)
/external/llvm-project/clang/test/SemaOpenCL/
Dvec_step.cl24 int res9[vec_step(int4) == 4 ? 1 : -1];
/external/clang/test/SemaOpenCL/
Dvec_step.cl24 int res9[vec_step(int4) == 4 ? 1 : -1];
/external/ethtool/
Dfec_8xx.c42 uint32_t res9[0x1e]; /* reserved */ member
/external/libaom/libaom/av1/common/arm/
Dwiener_convolve_neon.c83 uint16x8_t res5, res6, res7, res8, res9, res10, res11; in av1_wiener_convolve_add_src_neon() local
157 res9 = wiener_convolve8_horiz_8x8(res0, res1, res2, res3, filter_x_tmp, in av1_wiener_convolve_add_src_neon()
174 transpose_u16_8x8(&res4, &res5, &res6, &res7, &res8, &res9, &res10, in av1_wiener_convolve_add_src_neon()
176 store_u16_8x8(d_tmp, MAX_SB_SIZE, res4, res5, res6, res7, res8, res9, in av1_wiener_convolve_add_src_neon()
Djnt_convolve_neon.c1139 uint16x8_t res9, res10, res11; in av1_dist_wtd_convolve_x_neon() local
1226 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_x_neon()
1229 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res0), in av1_dist_wtd_convolve_x_neon()
1239 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_x_neon()
1242 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res4), in av1_dist_wtd_convolve_x_neon()
1574 uint16x8_t res10, res11, res9; in av1_dist_wtd_convolve_y_neon() local
1651 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_y_neon()
1654 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res0), in av1_dist_wtd_convolve_y_neon()
1664 load_u16_8x4(d_tmp, dst_stride, &res8, &res9, &res10, &res11); in av1_dist_wtd_convolve_y_neon()
1667 compute_avg_8x4(res8, res9, res10, res11, vreinterpretq_u16_s16(res4), in av1_dist_wtd_convolve_y_neon()
/external/llvm-project/polly/test/Isl/CodeGen/
Dinvariant_load_base_pointer_conditional_2.ll35 ; IR-NEXT: %.res9 = extractvalue { i64, i1 } %21, 0
36 ; IR-NEXT: %22 = icmp sge i64 %.res9, -2147483648
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-sadd-08.ll248 %res9 = or i1 %res8, %obit9
252 %res10 = or i1 %res9, %obit10
380 %res9 = or i1 %res8, %obit9
384 %res10 = or i1 %res9, %obit10
Dint-sadd-09.ll248 %res9 = or i1 %res8, %obit9
252 %res10 = or i1 %res9, %obit10
380 %res9 = or i1 %res8, %obit9
384 %res10 = or i1 %res9, %obit10
Dint-ssub-09.ll248 %res9 = or i1 %res8, %obit9
252 %res10 = or i1 %res9, %obit10
380 %res9 = or i1 %res8, %obit9
384 %res10 = or i1 %res9, %obit10
Dint-usub-10.ll248 %res9 = or i1 %res8, %obit9
252 %res10 = or i1 %res9, %obit10
380 %res9 = or i1 %res8, %obit9
384 %res10 = or i1 %res9, %obit10

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