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Searched refs:reserveRegisterTuples (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.cpp37 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
38 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
39 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
40 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
41 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
42 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::PV_X); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ALU_CONST); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); in getReservedRegs()
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DSIRegisterInfo.cpp144 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
145 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
148 reserveRegisterTuples(Reserved, AMDGPU::M0); in getReservedRegs()
151 reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ); in getReservedRegs()
152 reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ); in getReservedRegs()
153 reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC); in getReservedRegs()
156 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); in getReservedRegs()
157 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); in getReservedRegs()
158 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); in getReservedRegs()
159 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT); in getReservedRegs()
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DAMDGPURegisterInfo.h33 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
DR600RegisterInfo.h51 void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
DAMDGPURegisterInfo.cpp84 void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { in reserveRegisterTuples() function in AMDGPURegisterInfo
DR600InstrInfo.cpp1104 TRI.reserveRegisterTuples(Reserved, Reg); in reserveIndirectRegisters()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.cpp44 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
46 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
47 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
48 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
49 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
50 reserveRegisterTuples(Reserved, R600::PV_X); in getReservedRegs()
51 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); in getReservedRegs()
52 reserveRegisterTuples(Reserved, R600::ALU_CONST); in getReservedRegs()
53 reserveRegisterTuples(Reserved, R600::PREDICATE_BIT); in getReservedRegs()
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DSIRegisterInfo.cpp114 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, in reserveRegisterTuples() function in SIRegisterInfo
216 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
217 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
220 reserveRegisterTuples(Reserved, AMDGPU::M0); in getReservedRegs()
223 reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ); in getReservedRegs()
224 reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ); in getReservedRegs()
225 reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC); in getReservedRegs()
228 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); in getReservedRegs()
229 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); in getReservedRegs()
230 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); in getReservedRegs()
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DR600RegisterInfo.h54 void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
DSIRegisterInfo.h48 void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
DR600InstrInfo.cpp1105 TRI.reserveRegisterTuples(Reserved, Reg); in reserveIndirectRegisters()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp113 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { in reserveRegisterTuples() function in SIRegisterInfo
151 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
152 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
155 reserveRegisterTuples(Reserved, AMDGPU::TBA); in getReservedRegs()
156 reserveRegisterTuples(Reserved, AMDGPU::TMA); in getReservedRegs()
157 reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1); in getReservedRegs()
158 reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3); in getReservedRegs()
159 reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5); in getReservedRegs()
160 reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7); in getReservedRegs()
161 reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9); in getReservedRegs()
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DSIRegisterInfo.h33 void reserveRegisterTuples(BitVector &, unsigned Reg) const;