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Searched refs:ret4 (Results 1 – 25 of 26) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/
Dfast-isel-ret.ll35 define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
37 ; CHECK: ret4
/external/llvm/test/CodeGen/ARM/
Dfast-isel-ret.ll35 define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
37 ; CHECK: ret4
/external/llvm-project/libcxx/test/std/input.output/filesystems/class.path/path.member/
Dpath.compare.pass.cpp98 int ret4 = normalize_ret(p1.compare(RV)); in test_compare_basic() local
103 assert(ret1 == ret4); in test_compare_basic()
/external/libcxx/test/std/input.output/filesystems/class.path/path.member/
Dpath.compare.pass.cpp100 int ret4 = normalize_ret(p1.compare(RV)); in test_compare_basic() local
105 ASSERT_EQ(ret1, ret4); in test_compare_basic()
/external/llvm-project/clang/test/CodeGen/
Dppc32-and-aix-struct-return.c72 Four ret4(void) { return (Four){0.4}; } in ret4() function
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfast-isel-ret.ll51 define signext i16 @ret4(i16 signext %a) nounwind {
53 ; ELF64-LABEL: ret4
Dppc64-i128-abi.ll268 ; %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2)
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-ret.ll55 define signext i16 @ret4(i16 signext %a) nounwind {
57 ; ELF64-LABEL: ret4
Dppc64-i128-abi.ll224 ; %ret4 = call i128 @i128_increment_by_val(i128 %tmp2, i128 %tmp2)
/external/llvm-project/clang/test/SemaCUDA/
Dfunction-overload.cu397 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_single_side_overloading() local
410 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_wrong_side_overloading_inline_no_diag() local
423 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_wrong_side_overloading_inline_diag() local
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dbswap-02.ll121 %ret4 = add i32 %ret3, %swapped4
122 %ret5 = add i32 %ret4, %swapped5
Dbswap-03.ll121 %ret4 = add i64 %ret3, %swapped4
122 %ret5 = add i64 %ret4, %swapped5
/external/llvm-project/llvm/test/CodeGen/X86/
Dvar-permute-256.ll126 %ret4 = insertelement <8 x i32> %ret3, i32 %v4, i32 4
127 %ret5 = insertelement <8 x i32> %ret4, i32 %v5, i32 5
250 %ret4 = insertelement <16 x i16> %ret3, i16 %v4, i32 4
251 %ret5 = insertelement <16 x i16> %ret4, i16 %v5, i32 5
403 %ret4 = insertelement <32 x i8> %ret3, i8 %v4, i32 4
404 %ret5 = insertelement <32 x i8> %ret4, i8 %v5, i32 5
546 %ret4 = insertelement <8 x float> %ret3, float %v4, i32 4
547 %ret5 = insertelement <8 x float> %ret4, float %v5, i32 5
798 %ret4 = insertelement <16 x i16> %ret3, i16 %v4, i32 4
799 %ret5 = insertelement <16 x i16> %ret4, i16 %v5, i32 5
[all …]
Dvar-permute-128.ll219 %ret4 = insertelement <8 x i16> %ret3, i16 %v4, i32 4
220 %ret5 = insertelement <8 x i16> %ret4, i16 %v5, i32 5
362 %ret4 = insertelement <16 x i8> %ret3, i8 %v4, i32 4
363 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
627 %ret4 = insertelement <16 x i8> %ret3, i8 %v4, i32 4
628 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
1090 %ret4 = insertelement <16 x i8> %ret3, i8 %v4, i32 4
1091 %ret5 = insertelement <16 x i8> %ret4, i8 %v5, i32 5
Dvar-permute-512.ll31 %ret4 = insertelement <8 x i64> %ret3, i64 %v4, i32 4
32 %ret5 = insertelement <8 x i64> %ret4, i64 %v5, i32 5
79 %ret4 = insertelement <16 x i32> %ret3, i32 %v4, i32 4
80 %ret5 = insertelement <16 x i32> %ret4, i32 %v5, i32 5
292 %ret4 = insertelement <32 x i16> %ret3, i16 %v4, i32 4
293 %ret5 = insertelement <32 x i16> %ret4, i16 %v5, i32 5
910 %ret4 = insertelement <64 x i8> %ret3, i8 %v4, i32 4
911 %ret5 = insertelement <64 x i8> %ret4, i8 %v5, i32 5
998 %ret4 = insertelement <8 x double> %ret3, double %v4, i32 4
999 %ret5 = insertelement <8 x double> %ret4, double %v5, i32 5
[all …]
/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll110 %ret4 = add i32 %ret3, %val5
111 %ret5 = add i32 %ret4, %val6
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Denvreg.ll110 %ret4 = add i32 %ret3, %val5
111 %ret5 = add i32 %ret4, %val6
/external/llvm-project/llvm/test/Transforms/Attributor/
Dinternalize.ll120 %ret4 = call i32 @inner4(i32 %ret3, i32 %ret3)
121 ret i32 %ret4
/external/clang/test/SemaCUDA/
Dfunction-overload.cu380 HostReturnTy2 ret4 = host_only_function(1.0f); in test_host_device_single_side_overloading() local
/external/compiler-rt/test/dfsan/
Dcustom.cc536 int ret4 = inet_pton(AF_INET, addr4, &in4); in test_inet_pton() local
537 assert(ret4 == 1); in test_inet_pton()
/external/llvm-project/compiler-rt/test/dfsan/
Dcustom.cpp606 int ret4 = inet_pton(AF_INET, addr4, &in4); in test_inet_pton() local
607 assert(ret4 == 1); in test_inet_pton()
/external/llvm/test/CodeGen/X86/
Davx512bw-intrinsics.ll80 %ret4 = add i64 %ret3, %res4
82 %ret5 = add i64 %ret4, %res5
169 %ret4 = add i64 %ret3, %res4
171 %ret5 = add i64 %ret4, %res5
256 %ret4 = add i64 %ret3, %res4
258 %ret5 = add i64 %ret4, %res5
345 %ret4 = add i64 %ret3, %res4
347 %ret5 = add i64 %ret4, %res5
419 %ret4 = add i32 %ret3, %res4
421 %ret5 = add i32 %ret4, %res5
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td16 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
34 !if(!eq(size, 4), ret4,
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td58 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
77 !if(!eq(size, 4), ret4,
/external/tensorflow/tensorflow/python/kernel_tests/
Dwhile_v2_test.py563 ret4 = while_loop_v2(
573 return ret1, ret2, ret3, ret4, ret5

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