| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | fast-isel-ret.ll | 51 define i16 @ret6(i16 %a) nounwind uwtable ssp {
53 ; CHECK: ret6
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-ret.ll | 51 define i16 @ret6(i16 %a) nounwind uwtable ssp {
53 ; CHECK: ret6
|
| /external/llvm/test/CodeGen/X86/ |
| D | avx-splat.ll | 90 %ret6.i1245 = insertelement <8 x i32> undef, i32 %val.i1238, i32 6
91 %ret7.i1246 = insertelement <8 x i32> %ret6.i1245, i32 %val.i1238, i32 7
107 %ret6 = insertelement <8 x i32> undef, i32 %val, i32 6
108 %ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7
|
| D | avx512bw-intrinsics.ll | 84 %ret6 = add i64 %ret5, %res6
86 %ret7 = add i64 %ret6, %res7
173 %ret6 = add i64 %ret5, %res6
175 %ret7 = add i64 %ret6, %res7
260 %ret6 = add i64 %ret5, %res6
262 %ret7 = add i64 %ret6, %res7
349 %ret6 = add i64 %ret5, %res6
351 %ret7 = add i64 %ret6, %res7
423 %ret6 = add i32 %ret5, %res6
425 %ret7 = add i32 %ret6, %res7
[all …]
|
| /external/llvm-project/clang/test/CodeGen/ |
| D | ppc32-and-aix-struct-return.c | 80 Six ret6(void) { return (Six){12, 34, 56}; } in ret6() function
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | fast-isel-ret.ll | 67 define i16 @ret6(i16 %a) nounwind {
69 ; ELF64-LABEL: ret6
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | avx-splat.ll | 118 %ret6.i1245 = insertelement <8 x i32> undef, i32 %val.i1238, i32 6
119 %ret7.i1246 = insertelement <8 x i32> %ret6.i1245, i32 %val.i1238, i32 7
140 %ret6 = insertelement <8 x i32> undef, i32 %val, i32 6
141 %ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7
|
| D | var-permute-256.ll | 128 %ret6 = insertelement <8 x i32> %ret5, i32 %v6, i32 6
129 %ret7 = insertelement <8 x i32> %ret6, i32 %v7, i32 7
252 %ret6 = insertelement <16 x i16> %ret5, i16 %v6, i32 6
253 %ret7 = insertelement <16 x i16> %ret6, i16 %v7, i32 7
405 %ret6 = insertelement <32 x i8> %ret5, i8 %v6, i32 6
406 %ret7 = insertelement <32 x i8> %ret6, i8 %v7, i32 7
548 %ret6 = insertelement <8 x float> %ret5, float %v6, i32 6
549 %ret7 = insertelement <8 x float> %ret6, float %v7, i32 7
800 %ret6 = insertelement <16 x i16> %ret5, i16 %v6, i32 6
801 %ret7 = insertelement <16 x i16> %ret6, i16 %v7, i32 7
[all …]
|
| D | var-permute-128.ll | 221 %ret6 = insertelement <8 x i16> %ret5, i16 %v6, i32 6
222 %ret7 = insertelement <8 x i16> %ret6, i16 %v7, i32 7
364 %ret6 = insertelement <16 x i8> %ret5, i8 %v6, i32 6
365 %ret7 = insertelement <16 x i8> %ret6, i8 %v7, i32 7
629 %ret6 = insertelement <16 x i8> %ret5, i8 %v6, i32 6
630 %ret7 = insertelement <16 x i8> %ret6, i8 %v7, i32 7
1092 %ret6 = insertelement <16 x i8> %ret5, i8 %v6, i32 6
1093 %ret7 = insertelement <16 x i8> %ret6, i8 %v7, i32 7
|
| D | var-permute-512.ll | 33 %ret6 = insertelement <8 x i64> %ret5, i64 %v6, i32 6
34 %ret7 = insertelement <8 x i64> %ret6, i64 %v7, i32 7
81 %ret6 = insertelement <16 x i32> %ret5, i32 %v6, i32 6
82 %ret7 = insertelement <16 x i32> %ret6, i32 %v7, i32 7
294 %ret6 = insertelement <32 x i16> %ret5, i16 %v6, i32 6
295 %ret7 = insertelement <32 x i16> %ret6, i16 %v7, i32 7
912 %ret6 = insertelement <64 x i8> %ret5, i8 %v6, i32 6
913 %ret7 = insertelement <64 x i8> %ret6, i8 %v7, i32 7
1000 %ret6 = insertelement <8 x double> %ret5, double %v6, i32 6
1001 %ret7 = insertelement <8 x double> %ret6, double %v7, i32 7
[all …]
|
| D | avx512bw-intrinsics-upgrade.ll | 1937 %ret6 = add i64 %ret5, %res6
1939 %ret7 = add i64 %ret6, %res7
2056 %ret6 = add i64 %ret5, %res6
2058 %ret7 = add i64 %ret6, %res7
2149 %ret6 = add i64 %ret5, %res6
2151 %ret7 = add i64 %ret6, %res7
2268 %ret6 = add i64 %ret5, %res6
2270 %ret7 = add i64 %ret6, %res7
2332 %ret6 = add i32 %ret5, %res6
2334 %ret7 = add i32 %ret6, %res7
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | fast-isel-ret.ll | 71 define i16 @ret6(i16 %a) nounwind {
73 ; ELF64-LABEL: ret6
|
| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | bswap-02.ll | 123 %ret6 = add i32 %ret5, %swapped6
124 %ret7 = add i32 %ret6, %swapped7
|
| D | bswap-03.ll | 123 %ret6 = add i64 %ret5, %swapped6
124 %ret7 = add i64 %ret6, %swapped7
|
| /external/llvm/test/CodeGen/NVPTX/ |
| D | envreg.ll | 112 %ret6 = add i32 %ret5, %val7
113 %ret7 = add i32 %ret6, %val8
|
| /external/llvm-project/llvm/test/CodeGen/NVPTX/ |
| D | envreg.ll | 112 %ret6 = add i32 %ret5, %val7
113 %ret7 = add i32 %ret6, %val8
|
| /external/compiler-rt/test/dfsan/ |
| D | custom.cc | 544 int ret6 = inet_pton(AF_INET6, addr6, &in6); in test_inet_pton() local
545 assert(ret6 == 1); in test_inet_pton()
|
| /external/llvm-project/compiler-rt/test/dfsan/ |
| D | custom.cpp | 614 int ret6 = inet_pton(AF_INET6, addr6, &in6); in test_inet_pton() local
615 assert(ret6 == 1); in test_inet_pton()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 60 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5];
79 !if(!eq(size, 6), ret6,
|