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Searched refs:rlen (Results 1 – 25 of 165) sorted by relevance

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/external/mesa3d/src/intel/tools/tests/gen9/
Dsend.asm2 urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT };
4 urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q };
6 urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT };
8 const MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H };
10 urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT };
12 … thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT };
14 … sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
16 … sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
18 urb MsgDesc: 2 SIMD8 read mlen 1 rlen 4 { align1 1Q };
20 urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
[all …]
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
10 … sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
12 … sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
14 … sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };
16 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
18 … sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT };
20 … sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT };
[all …]
Dsends.asm2 …: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
4 …c: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q };
6 …: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
8 …a 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
10 … 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
12 …DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
14 …MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
16 …: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
18 …c: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q };
20 … ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dsend.asm2 math MsgDesc: inv mlen 1 rlen 1 { align1 compr };
4 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
6 math MsgDesc: inv mlen 1 rlen 1 { align16 };
8 … urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
10 … urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
12 … write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 };
14 … read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 };
16 … urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
18 sampler MsgDesc: (1, 0, 0, ) mlen 7 rlen 8 { align1 };
20 sampler MsgDesc: (1, 0, 0, ) mlen 5 rlen 8 { align1 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4/
Dsend.asm2 math MsgDesc: inv mlen 1 rlen 1 { align1 };
4 math MsgDesc: inv mlen 1 rlen 1 { align1 sechalf };
6 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
8 … urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
10 … urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
12 … write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 };
14 … read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 };
16 … urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
18 sampler MsgDesc: (1, 0, 0, F) mlen 7 rlen 8 { align1 };
20 sampler MsgDesc: (1, 0, 0, F) mlen 5 rlen 8 { align1 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dsend.asm2 … urb MsgDesc: 0 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
4 … urb MsgDesc: 0 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
6 … sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
8 … sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
10 … urb MsgDesc: 2 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
12 … urb MsgDesc: 3 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
14 … urb MsgDesc: 2 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
16 … urb MsgDesc: 1 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
18 … urb MsgDesc: 0 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
20 … urb MsgDesc: 1 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
[all …]
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
12 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
14 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
16 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
18 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
20 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dsend.asm2 … urb MsgDesc: 0 urb_write interleave used complete mlen 3 rlen 0 { align16 1Q EOT };
4 … urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 1Q EOT };
6 … sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
8 … sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
10 … render MsgDesc: OWORD dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 0 { align16 1Q };
12 … render MsgDesc: OWORD dual block read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 1Q };
14 … urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 1Q EOT };
16 … sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 11 rlen 4 { align1 1Q };
18 … sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
20 … sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
[all …]
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
12 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
14 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
16 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
18 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
20 render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen8/
Dsend.asm2 urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT };
4 urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q };
6 urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT };
8 const MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H };
10 urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT };
12 … 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
14 …a 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };
16 … thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT };
18 … sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
20 … sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
[all …]
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
12 … render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
14 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
16 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
18 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
20 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dsend.asm2 math MsgDesc: inv mlen 1 rlen 1 { align1 };
4 … write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
6 math MsgDesc: inv mlen 1 rlen 1 { align1 compr };
8 … write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
10 … urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
12 … sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 };
14 … sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 };
16 … sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 };
18 … sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 };
20 … read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 1 { align16 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dsend.asm2 … urb MsgDesc: 0 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
4 … urb MsgDesc: 0 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
6 … sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
8 … sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
10 … urb MsgDesc: 2 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
12 … urb MsgDesc: 3 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
14 … urb MsgDesc: 2 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
16 … urb MsgDesc: 1 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
18 … urb MsgDesc: 0 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
20 … urb MsgDesc: 1 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
[all …]
Dsendc.asm2 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
4 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
6 … render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
8 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
10 … render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
12 render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
14 … render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
16 … render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
18 … render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
20 … render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
[all …]
/external/libwebsockets/lib/roles/http/server/
Dfops-zip.c498 lws_filepos_t ramount, rlen, cur = lws_vfs_tell(fd); in lws_fops_zip_read() local
514 rlen = len; in lws_fops_zip_read()
515 if (rlen > fd->pos - priv->exp_uncomp_pos) in lws_fops_zip_read()
516 rlen = fd->pos - priv->exp_uncomp_pos; in lws_fops_zip_read()
517 if (lws_fops_zip_read(fd, amount, buf, rlen)) in lws_fops_zip_read()
528 rlen = sizeof(priv->rbuf); in lws_fops_zip_read()
529 if (rlen > priv->hdr.comp_size - in lws_fops_zip_read()
531 rlen = priv->hdr.comp_size - in lws_fops_zip_read()
537 rlen)) in lws_fops_zip_read()
580 rlen = sizeof(hd) - fd->pos; in lws_fops_zip_read()
[all …]
/external/tcpdump/
Dprint-forces.c394 #define GO_NXT_TLV(tlv,rlen) ((rlen) -= F_ALN_LEN(EXTRACT_16BITS(&(tlv)->length)), \ argument
401 #define GO_NXT_ILV(ilv,rlen) ((rlen) -= F_ALN_LEN(EXTRACT_32BITS(&(ilv)->length)), \ argument
417 static inline u_int tlv_valid(const struct forces_tlv *tlv, u_int rlen) in tlv_valid() argument
419 if (rlen < TLV_HDRL) in tlv_valid()
423 if (EXTRACT_16BITS(&tlv->length) > rlen) in tlv_valid()
425 if (rlen < F_ALN_LEN(EXTRACT_16BITS(&tlv->length))) in tlv_valid()
431 static inline int ilv_valid(const struct forces_ilv *ilv, u_int rlen) in ilv_valid() argument
433 if (rlen < ILV_HDRL) in ilv_valid()
437 if (EXTRACT_32BITS(&ilv->length) > rlen) in ilv_valid()
439 if (rlen < F_ALN_LEN(EXTRACT_32BITS(&ilv->length))) in ilv_valid()
[all …]
/external/strace/
Dnet.c226 int ulen, rlen; in decode_sockname() local
244 if (syserror(tcp) || umove(tcp, tcp->u_arg[2], &rlen) < 0) { in decode_sockname()
248 decode_sockaddr(tcp, tcp->u_arg[1], ulen > rlen ? rlen : ulen); in decode_sockname()
249 if (ulen != rlen) in decode_sockname()
250 tprintf(", [%d->%d]", ulen, rlen); in decode_sockname()
252 tprintf(", [%d]", rlen); in decode_sockname()
326 int ulen, rlen; in SYS_FUNC() local
350 if (!fetch_socklen(tcp, &rlen, tcp->u_arg[4], tcp->u_arg[5])) { in SYS_FUNC()
366 decode_sockaddr(tcp, tcp->u_arg[4], ulen > rlen ? rlen : ulen); in SYS_FUNC()
368 if (ulen != rlen) in SYS_FUNC()
[all …]
/external/openssh/
Dsshbuf.c219 size_t rlen; in sshbuf_set_max_size() local
236 rlen = SSHBUF_SIZE_INIT; in sshbuf_set_max_size()
238 rlen = ROUNDUP(buf->size, SSHBUF_SIZE_INC); in sshbuf_set_max_size()
239 if (rlen > max_size) in sshbuf_set_max_size()
240 rlen = max_size; in sshbuf_set_max_size()
241 SSHBUF_DBG(("new alloc = %zu", rlen)); in sshbuf_set_max_size()
242 if ((dp = recallocarray(buf->d, buf->alloc, rlen, 1)) == NULL) in sshbuf_set_max_size()
245 buf->alloc = rlen; in sshbuf_set_max_size()
305 size_t rlen, need; in sshbuf_allocate() local
326 rlen = ROUNDUP(buf->alloc + need, SSHBUF_SIZE_INC); in sshbuf_allocate()
[all …]
/external/libxml2/doc/examples/
Dio1.c24 static int rlen; variable
55 rlen = strlen(result); in sqlOpen()
71 rlen = 0; in sqlClose()
92 if (len > rlen) len = rlen; in sqlRead()
94 rlen -= len; in sqlRead()
/external/wpa_supplicant_8/src/eap_server/
Deap_server_gtc.c98 size_t rlen; in eap_gtc_process() local
100 pos = eap_hdr_validate(EAP_VENDOR_IETF, EAP_TYPE_GTC, respData, &rlen); in eap_gtc_process()
101 if (pos == NULL || rlen < 1) in eap_gtc_process()
104 wpa_hexdump_ascii_key(MSG_MSGDUMP, "EAP-GTC: Response", pos, rlen); in eap_gtc_process()
110 if (rlen < 10) { in eap_gtc_process()
117 end = pos + rlen; in eap_gtc_process()
161 rlen = end - pos; in eap_gtc_process()
164 pos, rlen); in eap_gtc_process()
176 if (rlen != sm->user->password_len || in eap_gtc_process()
177 os_memcmp_const(pos, sm->user->password, rlen) != 0) { in eap_gtc_process()
/external/libcxx/test/std/strings/string.view/string.view.ops/
Dcopy.pass.cpp30 const size_t rlen = std::min ( n, sv.size() - pos ); in test1() local
32 CharT *dest1 = new CharT [rlen + 1]; dest1[rlen] = 0; in test1()
33 CharT *dest2 = new CharT [rlen + 1]; dest2[rlen] = 0; in test1()
47 std::copy_n(sv.begin() + pos, rlen, dest2); in test1()
48 for ( size_t i = 0; i <= rlen; ++i ) in test1()
/external/llvm-project/libcxx/test/std/strings/string.view/string.view.ops/
Dcopy.pass.cpp29 const size_t rlen = std::min ( n, sv.size() - pos ); in test1() local
31 CharT *dest1 = new CharT [rlen + 1]; dest1[rlen] = 0; in test1()
32 CharT *dest2 = new CharT [rlen + 1]; dest2[rlen] = 0; in test1()
46 std::copy_n(sv.begin() + pos, rlen, dest2); in test1()
47 for ( size_t i = 0; i <= rlen; ++i ) in test1()
/external/python/cpython2/Lib/
Dbinhex.py61 rlen = fp.tell()
62 return file, finfo, dlen, rlen
175 name, finfo, dlen, rlen = name_finfo_dlen_rlen
186 self.rlen = rlen
199 d4 = struct.pack('>ii', self.dlen, self.rlen)
226 raise Error, 'Incorrect data size, diff=%r' % (self.rlen,)
235 self.rlen = self.rlen - len(data)
246 if self.rlen != 0:
248 "Incorrect resource-datasize, diff=%r" % (self.rlen,)
426 self.rlen = struct.unpack('>l', rest[15:19])[0]
[all …]
/external/wpa_supplicant_8/src/tls/
Dtlsv1_server_write.c47 size_t rlen; in tls_write_server_hello() local
175 &rlen) < 0) { in tls_write_server_hello()
181 pos = rhdr + rlen; in tls_write_server_hello()
193 size_t rlen; in tls_write_server_certificate() local
265 &rlen) < 0) { in tls_write_server_certificate()
271 pos = rhdr + rlen; in tls_write_server_certificate()
288 size_t rlen; in tls_write_server_certificate_status() local
352 &rlen) < 0) { in tls_write_server_certificate_status()
358 pos = rhdr + rlen; in tls_write_server_certificate_status()
374 size_t rlen; in tls_write_server_key_exchange() local
[all …]
/external/python/cpython3/Lib/
Dbinhex.py161 name, finfo, dlen, rlen = name_finfo_dlen_rlen
175 self.rlen = rlen
197 d4 = struct.pack('>ii', self.dlen, self.rlen)
224 raise Error('Incorrect data size, diff=%r' % (self.rlen,))
233 self.rlen = self.rlen - len(data)
244 if self.rlen != 0:
245 raise Error("Incorrect resource-datasize, diff=%r" % (self.rlen,))
421 self.rlen = struct.unpack('>l', rest[15:19])[0]
460 n = min(n, self.rlen)
462 n = self.rlen
[all …]

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