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Searched refs:rotl (Results 1 – 25 of 107) sorted by relevance

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/external/llvm-project/libcxx/test/std/numerics/bit/bitops.rot/
Drotl.pass.cpp32 return std::rotl(T(1), 0) == T( 1) in constexpr_test()
33 && std::rotl(T(1), 1) == T( 2) in constexpr_test()
34 && std::rotl(T(1), 2) == T( 4) in constexpr_test()
35 && std::rotl(T(1), 3) == T( 8) in constexpr_test()
36 && std::rotl(T(1), 4) == T( 16) in constexpr_test()
37 && std::rotl(T(1), 5) == T( 32) in constexpr_test()
38 && std::rotl(T(1), 6) == T( 64) in constexpr_test()
39 && std::rotl(T(1), 7) == T(128) in constexpr_test()
40 && std::rotl(max, 0) == max in constexpr_test()
41 && std::rotl(max, 1) == max in constexpr_test()
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/external/angle/third_party/abseil-cpp/absl/numeric/
Dbits_test.cc28 static_assert(rotl(uint8_t{0x12}, 0) == uint8_t{0x12}, ""); in TEST()
29 static_assert(rotl(uint16_t{0x1234}, 0) == uint16_t{0x1234}, ""); in TEST()
30 static_assert(rotl(uint32_t{0x12345678UL}, 0) == uint32_t{0x12345678UL}, ""); in TEST()
31 static_assert(rotl(uint64_t{0x12345678ABCDEF01ULL}, 0) == in TEST()
35 EXPECT_EQ(rotl(uint8_t{0x12}, 0), uint8_t{0x12}); in TEST()
36 EXPECT_EQ(rotl(uint16_t{0x1234}, 0), uint16_t{0x1234}); in TEST()
37 EXPECT_EQ(rotl(uint32_t{0x12345678UL}, 0), uint32_t{0x12345678UL}); in TEST()
38 EXPECT_EQ(rotl(uint64_t{0x12345678ABCDEF01ULL}, 0), in TEST()
41 EXPECT_EQ(rotl(uint8_t{0x12}, 8), uint8_t{0x12}); in TEST()
42 EXPECT_EQ(rotl(uint16_t{0x1234}, 16), uint16_t{0x1234}); in TEST()
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/external/llvm/test/CodeGen/SystemZ/
Drot-02.ll17 %rotl = or i32 %parta, %partb
19 ret i32 %rotl
33 %rotl = or i32 %parta, %partb
35 ret i32 %rotl
49 %rotl = or i32 %parta, %partb
51 ret i32 %rotl
65 %rotl = or i64 %parta, %partb
67 ret i64 %rotl
82 %rotl = or i32 %parta, %partb
84 %reuse = add i32 %and, %rotl
Drot-01.ll16 %rotl = or i32 %parta, %partb
18 ret i32 %rotl
32 %rotl = or i64 %parta, %partb
34 ret i64 %rotl
Drisbg-01.ll143 %rotl = or i32 %parta, %partb
144 %and = and i32 %rotl, 248
155 %rotl = or i64 %parta, %partb
156 %and = and i64 %rotl, 248
167 %rotl = or i32 %parta, %partb
168 %and = and i32 %rotl, 114688
179 %rotl = or i64 %parta, %partb
180 %and = and i64 %rotl, 114688
193 %rotl = or i32 %parta, %partb
194 %and = and i32 %rotl, 126
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/external/llvm-project/llvm/test/CodeGen/SystemZ/
Drot-02.ll20 %rotl = or i32 %parta, %partb
22 ret i32 %rotl
37 %rotl = or i32 %parta, %partb
39 ret i32 %rotl
54 %rotl = or i32 %parta, %partb
56 ret i32 %rotl
71 %rotl = or i64 %parta, %partb
73 ret i64 %rotl
90 %rotl = or i32 %parta, %partb
92 %reuse = add i32 %and, %rotl
Drot-01.ll19 %rotl = or i32 %parta, %partb
21 ret i32 %rotl
37 %rotl = or i64 %parta, %partb
39 ret i64 %rotl
Drisbg-04.ll157 %rotl = or i32 %parta, %partb
158 %and = and i32 %rotl, 248
170 %rotl = or i64 %parta, %partb
171 %and = and i64 %rotl, 248
183 %rotl = or i32 %parta, %partb
184 %and = and i32 %rotl, 114688
196 %rotl = or i64 %parta, %partb
197 %and = and i64 %rotl, 114688
211 %rotl = or i32 %parta, %partb
212 %and = and i32 %rotl, 126
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Drisbg-01.ll167 %rotl = or i32 %parta, %partb
168 %and = and i32 %rotl, 248
180 %rotl = or i64 %parta, %partb
181 %and = and i64 %rotl, 248
195 %rotl = or i32 %parta, %partb
196 %and = and i32 %rotl, 114688
208 %rotl = or i64 %parta, %partb
209 %and = and i64 %rotl, 114688
223 %rotl = or i32 %parta, %partb
224 %and = and i32 %rotl, 126
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/external/llvm-project/llvm/test/TableGen/
DSetTheory.td96 // The 'rotl' operator rotates left, but also accepts a negative shift.
97 def rotl;
98 def S6a : Set<(rotl S0f, 0)>;
99 def S6b : Set<(rotl S0f, 1)>;
100 def S6c : Set<(rotl S0f, 3)>;
101 def S6d : Set<(rotl S0f, 4)>;
102 def S6e : Set<(rotl S0f, 5)>;
103 def S6f : Set<(rotl S0f, -1)>;
104 def S6g : Set<(rotl S0f, -4)>;
105 def S6h : Set<(rotl S0f, -5)>;
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/external/llvm/test/TableGen/
DSetTheory.td96 // The 'rotl' operator rotates left, but also accepts a negative shift.
97 def rotl;
98 def S6a : Set<(rotl S0f, 0)>;
99 def S6b : Set<(rotl S0f, 1)>;
100 def S6c : Set<(rotl S0f, 3)>;
101 def S6d : Set<(rotl S0f, 4)>;
102 def S6e : Set<(rotl S0f, 5)>;
103 def S6f : Set<(rotl S0f, -1)>;
104 def S6g : Set<(rotl S0f, -4)>;
105 def S6h : Set<(rotl S0f, -5)>;
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/external/swiftshader/third_party/astc-encoder/Source/
Dastc_mathlib.cpp26 static inline uint64_t rotl(uint64_t val, int count) in rotl() function
45 state[0] = rotl(s0, 24) ^ s1 ^ (s1 << 16); in rand()
46 state[1] = rotl(s1, 37); in rand()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td131 let AltOrders = [(rotl GPR32common, 8)];
136 let AltOrders = [(rotl GPR64common, 8)];
141 let AltOrders = [(rotl GPR32, 8)];
145 let AltOrders = [(rotl GPR64, 8)];
151 let AltOrders = [(rotl GPR32sp, 8)];
155 let AltOrders = [(rotl GPR64sp, 8)];
414 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
416 [(rotl FPR64, 0), (rotl FPR64, 1),
417 (rotl FPR64, 2)]>;
419 [(rotl FPR64, 0), (rotl FPR64, 1),
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/external/rust/crates/ring/src/digest/
Dsha1.rs59 W[t] = rotl(wt, 1);
98 let T = rotl(a, 5) + f(b, c, d) + e + k + W_t;
101 c = rotl(b, 30);
109 fn rotl(x: W32, n: u32) -> W32 { in rotl() function
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td142 let AltOrders = [(rotl GPR32common, 8)];
147 let AltOrders = [(rotl GPR64common, 8)];
152 let AltOrders = [(rotl GPR32, 8)];
156 let AltOrders = [(rotl GPR64, 8)];
162 let AltOrders = [(rotl GPR32sp, 8)];
166 let AltOrders = [(rotl GPR64sp, 8)];
460 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
462 [(rotl FPR64, 0), (rotl FPR64, 1),
463 (rotl FPR64, 2)]>;
465 [(rotl FPR64, 0), (rotl FPR64, 1),
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td139 let AltOrders = [(rotl GPR32common, 8)];
144 let AltOrders = [(rotl GPR64common, 8)];
149 let AltOrders = [(rotl GPR32, 8)];
153 let AltOrders = [(rotl GPR64, 8)];
159 let AltOrders = [(rotl GPR32sp, 8)];
163 let AltOrders = [(rotl GPR64sp, 8)];
447 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
449 [(rotl FPR64, 0), (rotl FPR64, 1),
450 (rotl FPR64, 2)]>;
452 [(rotl FPR64, 0), (rotl FPR64, 1),
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/external/llvm-project/llvm/lib/Target/X86/
DX86InstrShiftRotate.td461 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
464 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16;
467 [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32;
470 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
475 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
478 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
482 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>,
487 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
492 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
495 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize16;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td461 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
464 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16;
467 [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32;
470 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
475 [(set GR8:$dst, (rotl GR8:$src1, (i8 relocImm:$src2)))]>;
478 [(set GR16:$dst, (rotl GR16:$src1, (i8 relocImm:$src2)))]>,
482 [(set GR32:$dst, (rotl GR32:$src1, (i8 relocImm:$src2)))]>,
487 [(set GR64:$dst, (rotl GR64:$src1, (i8 relocImm:$src2)))]>;
492 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
495 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize16;
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/external/llvm-project/llvm/test/Transforms/PhaseOrdering/
Drotate.ll9 define i32 @rotl(i32 %a, i32 %b) {
10 ; CHECK-LABEL: @rotl(
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td39 defm ROTL : BinaryInt<rotl, "rotl">;
69 def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>;
71 def : Pat<(rotl I64:$lhs, (and I64:$rhs, 63)), (ROTL_I64 I64:$lhs, I64:$rhs)>;
/external/llvm-project/llvm/test/CodeGen/AVR/
Drot.ll26 %rotl = or i8 %parta, %partb
28 ret i8 %rotl
/external/boringssl/src/crypto/fipsmodule/sha/asm/
Dsha1-586.pl173 &rotl($tmp1,5); # tmp1=ROTATE(a,5)
203 &rotl($f,1); # f=ROTATE(f,1)
209 &rotl($a,5); # ROTATE(a,5)
220 &rotl($f,1); # f=ROTATE(f,1)
226 &rotl($tmp1,5); # ROTATE(a,5)
247 &rotl($f,1); # f=ROTATE(f,1)
251 &rotl($a,5); # ROTATE(a,5)
265 &rotl($f,1); # f=ROTATE(f,1)
269 &rotl($tmp1,5); # ROTATE(a,5)
290 &rotl($f,1); # f=ROTATE(f,1)
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/external/llvm-project/llvm/test/CodeGen/RISCV/
Drotl-rotr.ll8 define i32 @rotl(i32 %x, i32 %y) nounwind {
9 ; RV32I-LABEL: rotl:
/external/boringssl/src/crypto/fipsmodule/md5/asm/
Dmd5-586.pl69 &rotl($a,$s);
94 &rotl($a,$s);
117 &rotl($a,$s);
140 &rotl($a,$s);
166 &rotl($a,$s);
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td473 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
476 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
479 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
482 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
487 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
490 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
494 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
499 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
505 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
509 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
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