| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | smml.ll | 59 ; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-const-a32.cc | 67 M(rscs) \
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| D | test-assembler-cond-rd-rn-operand-rm-a32.cc | 67 M(rscs) \
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 67 M(rscs) \
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 67 M(rscs) \
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| D | test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc | 67 M(rscs) \
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| D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 67 M(rscs) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 573 0xfe,0x1e,0xf8,0xe2 = rscs r1, r8, #4064
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2967 void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
2968 void rscs(Register rd, Register rn, const Operand& operand) { in rscs() function
2969 rscs(al, rd, rn, operand); in rscs()
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| D | disasm-aarch32.h | 1046 void rscs(Condition cond, Register rd, Register rn, const Operand& operand);
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| D | disasm-aarch32.cc | 2377 void Disassembler::rscs(Condition cond, in rscs() function in vixl::aarch32::Disassembler
58843 rscs(condition, in DecodeA32()
58862 rscs(condition, in DecodeA32()
60088 rscs(condition, in DecodeA32()
61317 rscs(condition, Register(rd), Register(rn), imm); in DecodeA32()
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| D | assembler-aarch32.cc | 9306 void Assembler::rscs(Condition cond, in rscs() function in vixl::aarch32::Assembler
9356 Delegate(kRscs, &Assembler::rscs, cond, rd, rn, operand); in rscs()
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| D | macro-assembler-aarch32.h | 3305 rscs(cond, rd, rn, operand); in Rscs()
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2106 rscs r1, r8, #4064
2150 @ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2076 rscs r1, r8, #4064
2120 @ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2]
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