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Searched refs:rsrc1 (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_shader.c913 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / in radv_postprocess_config()
921 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8); in radv_postprocess_config()
928 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
941 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
966 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | in radv_postprocess_config()
972 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
999 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
1005 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
1011 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | in radv_postprocess_config()
1017 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | in radv_postprocess_config()
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Dradv_pipeline.c4197 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_vs()
4260 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_es()
4283 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_ls()
4304 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_ngg()
4441 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_hs()
4447 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_hs()
4648 radeon_emit(cs, gs->config.rsrc1); in radv_pipeline_generate_hw_gs()
4657 radeon_emit(cs, gs->config.rsrc1); in radv_pipeline_generate_hw_gs()
4859 radeon_emit(cs, ps->config.rsrc1); in radv_pipeline_generate_fragment_shader()
5358 radeon_emit(cs, shader->config.rsrc1); in radv_pipeline_generate_hw_cs()
Dradv_device.c3806 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | in radv_get_preamble_cs() local
3809 map[1] = rsrc1; in radv_get_preamble_cs()
/external/mesa3d/src/amd/common/
Dac_binary.h48 unsigned rsrc1; member
Dac_binary.c62 conf->rsrc1 = value; in ac_parse_shader_binary_config()
Dac_rtld.c547 assert(config->rsrc1 == 0 && config->rsrc2 == 0); in ac_rtld_read_config()
548 config->rsrc1 = c.rsrc1; in ac_rtld_read_config()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers; in code_object_to_config() local
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1); in code_object_to_config()
102 out_config->rsrc1 = rsrc1; in code_object_to_config()
192 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) / in si_create_compute_state_async()
200 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8); in si_create_compute_state_async()
513 radeon_emit(cs, config->rsrc1); in si_switch_compute_shader()
519 config->rsrc1, config->rsrc2); in si_switch_compute_shader()
Dsi_state_shaders.c497 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_ls()
868 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | in si_shader_gs() local
882 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_gs()
886 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1); in si_shader_gs()
1457 uint32_t rsrc1 = in si_shader_vs() local
1471 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_vs()
1481 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1); in si_shader_vs()
1676 uint32_t rsrc1 = in si_shader_ps() local
1682 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8); in si_shader_ps()
1685 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1); in si_shader_ps()
Dsi_state_draw.c276 radeon_emit(cs, ls_current->config.rsrc1); in si_emit_derived_tess_state()