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Searched refs:rw_gpr (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DEvergreenInstructions.td50 : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,
52 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"
54 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,
59 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs),
60 "MSKOR $rw_gpr.XW, $index_gpr",
61 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
68 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {
70 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
72 name ## "_RTN" ## " $rw_gpr, $index_gpr", [] >;
74 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
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DCaymanInstructions.td77 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
78 "STORE_DWORD $rw_gpr, $index_gpr",
79 [(store_global vt:$rw_gpr, i32:$index_gpr)]> {
DR600InstrFormats.td468 bits<7> rw_gpr;
478 let Word0{21-15} = rw_gpr;
/external/llvm/lib/Target/AMDGPU/
DEvergreenInstructions.td44 : CF_MEM_RAT <0x1, ?, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,
46 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"
48 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,
53 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
54 "MSKOR $rw_gpr.XW, $index_gpr",
55 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
96 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
97 "STORE_RAW $rw_gpr, $index_gpr, $eop",
98 [(global_store i32:$rw_gpr, i32:$index_gpr)]
103 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
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DCaymanInstructions.td74 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
75 "STORE_DWORD $rw_gpr, $index_gpr",
76 [(global_store vt:$rw_gpr, i32:$index_gpr)]> {
DR600InstrFormats.td459 bits<7> rw_gpr;
469 let Word0{21-15} = rw_gpr;
/external/llvm-project/llvm/lib/Target/AMDGPU/
DEvergreenInstructions.td59 : CF_MEM_RAT <0x1, ?, 0xf, (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr,
61 "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr"
63 [(int_r600_rat_store_typed R600_Reg128:$rw_gpr,
68 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), (outs),
69 "MSKOR $rw_gpr.XW, $index_gpr",
70 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
77 let Constraints = "$rw_gpr = $out_gpr", eop = 0, mayStore = 1 in {
79 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
81 name # "_RTN $rw_gpr, $index_gpr", [] >;
83 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr),
[all …]
DCaymanInstructions.td78 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr),
79 "STORE_DWORD $rw_gpr, $index_gpr",
80 [(store_global vt:$rw_gpr, i32:$index_gpr)]> {
DR600InstrFormats.td468 bits<7> rw_gpr;
478 let Word0{21-15} = rw_gpr;
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_dump.cpp131 s << " R" << n.bc.rw_gpr << "-" << in dump()
132 n.bc.rw_gpr + n.bc.burst_count << "."; in dump()
135 s << " R" << n.bc.rw_gpr << "."; in dump()
147 s << " R" << n.bc.rw_gpr << "."; in dump()
Dsb_bc_parser.cpp809 c->src[s] = sh->get_gpr_value(true, c->bc.rw_gpr, in prepare_ir()
821 ++cf_next->bc.rw_gpr; in prepare_ir()
846 sh->get_gpr_value(true, c->bc.rw_gpr, s, false); in prepare_ir()
855 sh->get_gpr_value(true, c->bc.rw_gpr, s, false); in prepare_ir()
889 ++cf_next->bc.rw_gpr; in prepare_ir()
Dsb_bc_decoder.cpp185 bc.rw_gpr = w0.get_RW_GPR(); in decode_cf_exp()
240 bc.rw_gpr = w0.get_RW_GPR(); in decode_cf_mem()
248 bc.rw_gpr = w0.get_RW_GPR(); in decode_cf_mem()
Dsb_bc_builder.cpp275 .RW_GPR(bc.rw_gpr) in build_cf_exp()
284 .RW_GPR(bc.rw_gpr) in build_cf_exp()
Dsb_bc_finalize.cpp774 c->bc.rw_gpr = reg >= 0 ? reg : 0; in finalize_cf()
815 c->bc.rw_gpr = reg >= 0 ? reg : 0; in finalize_cf()
Dsb_bc.h465 unsigned rw_gpr:7; member