s_add_i32 (reference) in projects: external

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Searched refs:s_add_i32 (Results 1 – 25 of 125) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	add.ll	5 ; FUNC-LABEL: {{^}}s_add_i32: 6 ; GCN: s_add_i32 s[[REG:[0-9]+]], {{s[0-9]+, s[0-9]+}} 9 define amdgpu_kernel void @s_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 19 ; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 20 ; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 31 ; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 32 ; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 33 ; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 34 ; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} 45 ; GCN: s_add_i32 [all …]
D	cc-sgpr-limit.ll	`5 ; CHECK: s_add_i32 s0, s0, s1 6 ; CHECK: s_add_i32 s1, s0, s2 7 ; CHECK: s_add_i32 s2, s1, s3 8 ; CHECK: s_add_i32 s3, s2, s4 9 ; CHECK: s_add_i32 s4, s3, s5 10 ; CHECK: s_add_i32 s5, s4, s6 11 ; CHECK: s_add_i32 s6, s5, s7 12 ; CHECK: s_add_i32 s7, s6, s8 13 ; CHECK: s_add_i32 s8, s7, s9 14 ; CHECK: s_add_i32 s9, s8, s10 [all …]`
D	gep-address-space.ll	`18 ; CI: s_add_i32 27 ; SI: s_add_i32 28 ; SI: s_add_i32 29 ; SI: s_add_i32 30 ; SI: s_add_i32 56 ; SI: s_add_i32 57 ; SI: s_add_i32`
D	calling-conventions.ll	`185 ; VI: s_add_i32 s0, s0, 1 188 ; VI: s_add_i32 s0, s0, 0x10000 192 ; SI: s_add_i32 s0, s0, 1 195 ; SI: s_add_i32 s0, s0, 0x10000 234 ; GCN-DAG: s_add_i32 s0, s0, 1 235 ; GCN-DAG: s_add_i32 s{{[0-9]}}, s1, 2 236 ; GCN-DAG: s_add_i32 s{{[0-9]}}, s2, 3 254 ; GCN-DAG: s_add_i32 s0, s0, 1 255 ; GCN-DAG: s_add_i32 s{{[0-9]}}, s1, 2 256 ; GCN-DAG: s_add_i32 s{{[0-9]}}, s2, 3 [all …]`
D	32-bit-local-address-space.ll	`24 ; SI: s_add_i32 [[SPTR:s[0-9]]] 48 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 74 ; SI-NEXT: s_add_i32 113 ; SI: s_add_i32 [[SADDR:s[0-9]+]], 134 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004`
D	sgpr-control-flow.ll	`21 ; SI-NEXT: s_add_i32 s0, s11, s0 29 ; SI-NEXT: s_add_i32 s0, s0, s8 67 ; SI-NEXT: s_add_i32 s3, s3, s6 76 ; SI-NEXT: s_add_i32 s3, s3, s0 78 ; SI-NEXT: s_add_i32 s0, s3, s2 119 ; SI-NEXT: s_add_i32 s6, s2, s3 126 ; SI-NEXT: s_add_i32 s0, s0, s1`
D	reassoc-scalar.ll	`5 ; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 18 ; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 49 ; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 50 ; GCN: s_add_i32 [[ADD2:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 68 ; GCN: s_add_i32 [[ADD1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}`
D	non-entry-alloca.ll	`32 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 38 ; MUBUF-NEXT: s_add_i32 s6, s6, s7 69 ; FLATSCR-NEXT: s_add_i32 s4, s2, s3 76 ; FLATSCR-NEXT: s_add_i32 s4, s4, s2 134 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 141 ; MUBUF-NEXT: s_add_i32 s6, s6, s7 167 ; FLATSCR-NEXT: s_add_i32 s2, s32, 0x1000 174 ; FLATSCR-NEXT: s_add_i32 s2, s2, s3 229 ; MUBUF-NEXT: s_add_i32 s6, s32, 0x1000 267 ; FLATSCR-NEXT: s_add_i32 s4, s2, s3 [all …]`
D	early-if-convert.ll	`185 ; GCN: s_add_i32 247 ; GCN: s_add_i32 [[ADD:s[0-9]+]], [[VAL]], [[VAL]] 315 ; GCN: s_add_i32 316 ; GCN: s_add_i32 317 ; GCN: s_add_i32 340 ; GCN: s_add_i32 341 ; GCN: s_add_i32 342 ; GCN: s_add_i32 343 ; GCN: s_add_i32`
D	sminmax.ll	`8 ; GCN: s_add_i32 62 ; GCN: s_add_i32 63 ; GCN: s_add_i32 121 ; GCN: s_add_i32 122 ; GCN: s_add_i32 123 ; GCN: s_add_i32 124 ; GCN: s_add_i32`
D	s_addk_i32.ll	`22 ; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]] 23 ; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]] 99 ; SI: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8000{{$}}`
/external/llvm/test/CodeGen/AMDGPU/
D	add.ll	`66 ; SI: s_add_i32 67 ; SI: s_add_i32 68 ; SI: s_add_i32 69 ; SI: s_add_i32 70 ; SI: s_add_i32 71 ; SI: s_add_i32 72 ; SI: s_add_i32 73 ; SI: s_add_i32 99 ; SI: s_add_i32 100 ; SI: s_add_i32 [all …]`
D	gep-address-space.ll	`18 ; CI: s_add_i32 27 ; SI: s_add_i32 28 ; SI: s_add_i32 29 ; SI: s_add_i32 30 ; SI: s_add_i32 56 ; SI: s_add_i32 57 ; SI: s_add_i32`
D	32-bit-local-address-space.ll	`24 ; SI: s_add_i32 [[SPTR:s[0-9]]] 48 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004 72 ; SI-NEXT: s_add_i32 111 ; SI: s_add_i32 [[SADDR:s[0-9]+]], 132 ; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004`
D	sminmax.ll	`7 ; GCN: s_add_i32 38 ; GCN: s_add_i32 39 ; GCN: s_add_i32 89 ; GCN: s_add_i32 90 ; GCN: s_add_i32 91 ; GCN: s_add_i32 92 ; GCN: s_add_i32`
D	s_addk_i32.ll	`19 ; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]] 20 ; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]] 87 ; SI: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8000{{$}}`
D	shl_add_constant.ll	`60 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]] 76 ; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]] 77 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8`
D	indirect-addressing-si.ll	59 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}} 71 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}} 85 ; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}} 143 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}} 158 ; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}} 171 ; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}} 186 ; CHECK: s_add_i32 m0, m0, -{{[0-9]+}} 399 ; CHECK-DAG: s_add_i32 m0, [[ARG]], -16 402 ; CHECK: s_add_i32 m0, [[ARG]], -14 443 ; CHECK: s_add_i32 m0, [[IDX]], 4
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	add.v2i16.ll	`155 ; GFX9-NEXT: s_add_i32 s0, s0, 0xffc0ffc0 156 ; GFX9-NEXT: s_add_i32 s1, s1, 0xffc0 166 ; GFX8-NEXT: s_add_i32 s0, s0, s1 167 ; GFX8-NEXT: s_add_i32 s2, s2, s1 181 ; GFX9-NEXT: s_add_i32 s0, s0, 0x4ffc0 182 ; GFX9-NEXT: s_add_i32 s1, s1, 4 191 ; GFX8-NEXT: s_add_i32 s0, s0, 0xffc0 192 ; GFX8-NEXT: s_add_i32 s1, s1, 4 206 ; GFX9-NEXT: s_add_i32 s0, s0, 0xffc00004 207 ; GFX9-NEXT: s_add_i32 s1, s1, 0xffc0 [all …]`
D	mul.ll	`214 ; GFX7-NEXT: s_add_i32 s1, s1, s0 227 ; GFX8-NEXT: s_add_i32 s1, s1, s0 239 ; GFX9-NEXT: s_add_i32 s1, s1, s3 240 ; GFX9-NEXT: s_add_i32 s1, s1, s0 303 ; GFX7-NEXT: s_add_i32 s0, s2, s7 304 ; GFX7-NEXT: s_add_i32 s0, s0, s5 333 ; GFX8-NEXT: s_add_i32 s0, s2, s7 334 ; GFX8-NEXT: s_add_i32 s0, s0, s5 357 ; GFX9-NEXT: s_add_i32 s8, s8, s9 361 ; GFX9-NEXT: s_add_i32 s2, s2, s9 [all …]`
D	shlN_add.ll	`16 ; GFX8-NEXT: s_add_i32 s0, s0, s1 32 ; GFX8-NEXT: s_add_i32 s0, s0, s1 48 ; GFX8-NEXT: s_add_i32 s0, s0, s1 64 ; GFX8-NEXT: s_add_i32 s0, s0, s1 75 ; GCN-NEXT: s_add_i32 s0, s0, s1 275 ; GFX8-NEXT: s_add_i32 s0, s0, s2 276 ; GFX8-NEXT: s_add_i32 s1, s1, s3 294 ; GFX8-NEXT: s_add_i32 s0, s0, s2 295 ; GFX8-NEXT: s_add_i32 s1, s1, s3 313 ; GFX8-NEXT: s_add_i32 s0, s0, s2 [all …]`
/external/llvm-project/llvm/test/MC/AMDGPU/
D	literals.s	`537 s_add_i32 s0, vccz, s0 label 541 s_add_i32 s0, execz, s0 label 545 s_add_i32 s0, scc, s0 label 659 s_add_i32 s0, src_shared_base, s0 label 663 s_add_i32 s0, src_shared_limit, s0 label 667 s_add_i32 s0, src_private_base, s0 label 671 s_add_i32 s0, src_private_limit, s0 label 675 s_add_i32 s0, src_pops_exiting_wave_id, s0 label`
D	out-of-range-registers.s	`11 s_add_i32 s106, s0, s1 label 14 s_add_i32 s104, s0, s1 label 18 s_add_i32 s105, s0, s1 label`
/external/llvm/test/MC/AMDGPU/
D	out-of-range-registers.s	`4 s_add_i32 s104, s0, s1 label 7 s_add_i32 s105, s0, s1 label`
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
D	literal_gfx9.txt	6 # GFX9: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81] 9 # GFX9: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81] 12 # GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81] 15 # GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81] 18 # GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81] 84 # GFX9: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81] 87 # GFX9: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81] 90 # GFX9: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81]

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