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Searched refs:s_and_b32 (Results 1 – 25 of 176) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
Dtrap.s29 s_and_b32 ttmp10, ttmp8, 0x00000080 label
33 s_and_b32 ttmp9, tma_hi, 0x0000ffff label
37 s_and_b32 ttmp9, ttmp9, 0x000001ff label
41 s_and_b32 ttmp9, tma_lo, 0xffff0000 label
45 s_and_b32 ttmp9, ttmp9, ttmp8 label
49 s_and_b32 ttmp8, ttmp1, 0x01000000 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dtrap.s40 s_and_b32 ttmp10, ttmp8, 0x00000080 label
45 s_and_b32 ttmp9, tma_hi, 0x0000ffff label
50 s_and_b32 ttmp9, ttmp9, 0x000001ff label
55 s_and_b32 ttmp9, tma_lo, 0xffff0000 label
60 s_and_b32 ttmp9, ttmp9, ttmp8 label
65 s_and_b32 ttmp8, ttmp1, 0x01000000 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlshr.ll60 ; GFX6-NEXT: s_and_b32 s1, s1, s2
61 ; GFX6-NEXT: s_and_b32 s0, s0, s2
68 ; GFX8-NEXT: s_and_b32 s0, s0, s2
69 ; GFX8-NEXT: s_and_b32 s1, s1, s2
76 ; GFX9-NEXT: s_and_b32 s0, s0, s2
77 ; GFX9-NEXT: s_and_b32 s1, s1, s2
87 ; GCN-NEXT: s_and_b32 s0, s0, 0xff
123 ; GCN-NEXT: s_and_b32 s1, s1, s2
124 ; GCN-NEXT: s_and_b32 s0, s0, s2
134 ; GCN-NEXT: s_and_b32 s0, s0, 0xffffff
[all …]
Dshl.ll54 ; GFX6-NEXT: s_and_b32 s1, s1, 0xff
61 ; GFX8-NEXT: s_and_b32 s0, s0, s2
62 ; GFX8-NEXT: s_and_b32 s1, s1, s2
69 ; GFX9-NEXT: s_and_b32 s0, s0, s2
70 ; GFX9-NEXT: s_and_b32 s1, s1, s2
123 ; GCN-NEXT: s_and_b32 s1, s1, 0xffffff
398 ; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
405 ; GFX8-NEXT: s_and_b32 s0, s0, s2
406 ; GFX8-NEXT: s_and_b32 s1, s1, s2
413 ; GFX9-NEXT: s_and_b32 s0, s0, s2
[all …]
Dbool-legalization.ll9 ; GCN-NEXT: s_and_b32 s0, 1, s0
22 ; GCN-NEXT: s_and_b32 s0, s0, s1
23 ; GCN-NEXT: s_and_b32 s0, 1, s0
38 ; GCN-NEXT: s_and_b32 s0, s0, s1
39 ; GCN-NEXT: s_and_b32 s0, s0, 1
56 ; GCN-NEXT: s_and_b32 s0, s0, 1
83 ; GCN-NEXT: s_and_b32 s0, s0, s1
85 ; GCN-NEXT: s_and_b32 s0, s0, 1
Dinsertelement.i8.ll584 ; GFX9-NEXT: s_and_b32 s3, s3, 3
586 ; GFX9-NEXT: s_and_b32 s2, s2, s1
619 ; GFX8-NEXT: s_and_b32 s1, s3, 3
622 ; GFX8-NEXT: s_and_b32 s2, s2, s0
658 ; GFX7-NEXT: s_and_b32 s1, s3, 3
659 ; GFX7-NEXT: s_and_b32 s2, s2, s0
709 ; GFX9-NEXT: s_and_b32 s2, s2, s6
712 ; GFX9-NEXT: s_and_b32 s1, s1, s6
715 ; GFX9-NEXT: s_and_b32 s2, s3, s6
720 ; GFX9-NEXT: s_and_b32 s2, s4, 3
[all …]
Ddynamic-alloca-uniform.ll17 ; GFX9-NEXT: s_and_b32 s4, s4, -16
41 ; GFX10-NEXT: s_and_b32 s4, s4, -16
69 ; GFX9-NEXT: s_and_b32 s4, s4, -16
95 ; GFX10-NEXT: s_and_b32 s4, s4, -16
119 ; GFX9-NEXT: s_and_b32 s4, s4, -16
143 ; GFX10-NEXT: s_and_b32 s4, s4, -16
171 ; GFX9-NEXT: s_and_b32 s4, s4, -16
197 ; GFX10-NEXT: s_and_b32 s4, s4, -16
221 ; GFX9-NEXT: s_and_b32 s4, s4, -16
225 ; GFX9-NEXT: s_and_b32 s4, s4, 0xfffff800
[all …]
Dmul.ll15 ; GFX8-NEXT: s_and_b32 s0, s0, s2
16 ; GFX8-NEXT: s_and_b32 s1, s1, s2
23 ; GFX9-NEXT: s_and_b32 s0, s0, s2
24 ; GFX9-NEXT: s_and_b32 s1, s1, s2
60 ; GFX7-NEXT: s_and_b32 s0, s0, 0xffff
66 ; GFX8-NEXT: s_and_b32 s0, s0, s2
67 ; GFX8-NEXT: s_and_b32 s1, s1, s2
69 ; GFX8-NEXT: s_and_b32 s0, s0, s2
75 ; GFX9-NEXT: s_and_b32 s0, s0, s2
76 ; GFX9-NEXT: s_and_b32 s1, s1, s2
[all …]
Dandn2.ll289 ; GFX6-NEXT: s_and_b32 s2, s2, s1
293 ; GFX6-NEXT: s_and_b32 s1, s4, s1
296 ; GFX6-NEXT: s_and_b32 s0, s0, s1
313 ; GFX6-NEXT: s_and_b32 s2, s2, s1
317 ; GFX6-NEXT: s_and_b32 s1, s4, s1
320 ; GFX6-NEXT: s_and_b32 s0, s1, s0
337 ; GFX6-NEXT: s_and_b32 s2, s2, s1
341 ; GFX6-NEXT: s_and_b32 s1, s4, s1
344 ; GFX6-NEXT: s_and_b32 s0, s0, s1
367 ; GFX6-NEXT: s_and_b32 s2, s2, s1
[all …]
Dadd.v2i16.ll165 ; GFX8-NEXT: s_and_b32 s0, s0, s3
169 ; GFX8-NEXT: s_and_b32 s0, s0, s3
190 ; GFX8-NEXT: s_and_b32 s0, s0, s2
194 ; GFX8-NEXT: s_and_b32 s0, s0, s2
215 ; GFX8-NEXT: s_and_b32 s0, s0, s2
219 ; GFX8-NEXT: s_and_b32 s0, s0, s2
242 ; GFX8-NEXT: s_and_b32 s0, s0, s3
243 ; GFX8-NEXT: s_and_b32 s1, s1, s3
247 ; GFX8-NEXT: s_and_b32 s0, s0, s3
272 ; GFX8-NEXT: s_and_b32 s0, s0, s3
[all …]
Dorn2.ll289 ; GFX6-NEXT: s_and_b32 s2, s2, s1
293 ; GFX6-NEXT: s_and_b32 s1, s4, s1
313 ; GFX6-NEXT: s_and_b32 s2, s2, s1
317 ; GFX6-NEXT: s_and_b32 s1, s4, s1
337 ; GFX6-NEXT: s_and_b32 s2, s2, s1
341 ; GFX6-NEXT: s_and_b32 s1, s4, s1
367 ; GFX6-NEXT: s_and_b32 s2, s2, s1
369 ; GFX6-NEXT: s_and_b32 s3, s4, s1
373 ; GFX6-NEXT: s_and_b32 s1, s6, s1
460 ; GFX6-NEXT: s_and_b32 s1, s2, s3
[all …]
Dllvm.amdgcn.div.fmas.ll93 ; GFX7-NEXT: s_and_b32 s0, 1, s3
106 ; GFX8-NEXT: s_and_b32 s0, 1, s3
120 ; GFX10_W32-NEXT: s_and_b32 s3, 1, s3
131 ; GFX10_W64-NEXT: s_and_b32 s3, 1, s3
149 ; GFX7-NEXT: s_and_b32 s0, 1, s6
167 ; GFX8-NEXT: s_and_b32 s0, 1, s6
185 ; GFX10_W32-NEXT: s_and_b32 s6, 1, s6
198 ; GFX10_W64-NEXT: s_and_b32 s6, 1, s6
224 ; GFX7-NEXT: s_and_b32 s0, 1, s0
243 ; GFX8-NEXT: s_and_b32 s2, 1, s5
[all …]
Dashr.ll59 ; GFX6-NEXT: s_and_b32 s1, s1, 0xff
118 ; GCN-NEXT: s_and_b32 s1, s1, 0xffffff
396 ; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
453 ; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
534 ; GFX6-NEXT: s_and_b32 s2, s2, s4
537 ; GFX6-NEXT: s_and_b32 s2, s3, s4
540 ; GFX6-NEXT: s_and_b32 s1, s1, s4
541 ; GFX6-NEXT: s_and_b32 s0, s0, s4
557 ; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
612 ; GFX6-NEXT: s_and_b32 s0, s0, s2
[all …]
Dxnor.ll24 ; GFX7-NEXT: s_and_b32 s0, s0, s4
27 ; GFX7-NEXT: s_and_b32 s2, s2, s4
39 ; GFX8-NEXT: s_and_b32 s0, s0, s2
42 ; GFX8-NEXT: s_and_b32 s0, s0, s2
97 ; GFX7-NEXT: s_and_b32 s0, s0, s8
100 ; GFX7-NEXT: s_and_b32 s2, s2, s8
102 ; GFX7-NEXT: s_and_b32 s3, s4, s8
106 ; GFX7-NEXT: s_and_b32 s4, s6, s8
119 ; GFX8-NEXT: s_and_b32 s2, s0, s4
122 ; GFX8-NEXT: s_and_b32 s6, s1, s4
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dand.ll11 ; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
12 ; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
30 ; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
31 ; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
32 ; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
33 ; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
45 ; SI: s_and_b32
53 ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
61 ; can fold into the s_and_b32 and the VALU one is materialized
67 ; SI-DAG: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
[all …]
Dfabs.ll14 ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
27 ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
39 ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
51 ; GCN: s_and_b32
52 ; GCN: s_and_b32
65 ; GCN: s_and_b32
66 ; GCN: s_and_b32
67 ; GCN: s_and_b32
68 ; GCN: s_and_b32
Didot2.ll26 ; GFX7-NEXT: s_and_b32 s4, s4, s8
27 ; GFX7-NEXT: s_and_b32 s5, s5, s8
48 ; GFX8-NEXT: s_and_b32 s6, s3, s2
50 ; GFX8-NEXT: s_and_b32 s2, s4, s2
73 ; GFX9-NODL-NEXT: s_and_b32 s6, s3, s2
75 ; GFX9-NODL-NEXT: s_and_b32 s2, s4, s2
157 ; GFX7-NEXT: s_and_b32 s4, s4, s8
161 ; GFX7-NEXT: s_and_b32 s5, s5, s8
180 ; GFX8-NEXT: s_and_b32 s6, s3, s2
181 ; GFX8-NEXT: s_and_b32 s2, s4, s2
[all …]
Dllvm.amdgcn.raw.buffer.store.format.d16.ll19 ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
36 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
37 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
44 ; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
61 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
63 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
Dllvm.amdgcn.tbuffer.store.d16.ll19 ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
36 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
37 ; UNPACKED-DAG: s_and_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], [[K]]
43 ; PACKED-DAG: s_and_b32 [[SHR0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
58 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
60 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
Dllvm.amdgcn.struct.buffer.store.format.d16.ll19 ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
36 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
37 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
44 ; PACKED: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
61 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
63 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
Dllvm.amdgcn.raw.tbuffer.store.d16.ll22 ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
40 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
41 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
48 ; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
65 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
67 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
Dllvm.amdgcn.struct.tbuffer.store.d16.ll22 ; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
40 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
41 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
47 ; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
64 ; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], [[K]]
66 ; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], [[K]]
/external/llvm/test/CodeGen/AMDGPU/
Dand.ll44 ; SI: s_and_b32
52 ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
60 ; can fold into the s_and_b32 and the VALU one is materialized
66 ; SI-DAG: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
82 ; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
181 ; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}}
182 ; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}}
205 ; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}}
222 ; SI: s_and_b32 s{{[0-9]+}}, [[A]], 62
223 ; SI: s_and_b32 s{{[0-9]+}}, [[B]], 62
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_vi.txt22 # VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
25 # VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
28 # VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
31 # VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
34 # VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
37 # VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_vi.txt22 # VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
25 # VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
28 # VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
31 # VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
34 # VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
37 # VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]

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