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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsi-annotate-cf.ll18 ; SI-NEXT: s_and_b64 s[2:3], exec, vcc
42 ; FLAT-NEXT: s_and_b64 s[2:3], exec, vcc
80 ; SI-NEXT: s_and_b64 s[4:5], s[0:1], exec
85 ; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
104 ; FLAT-NEXT: s_and_b64 s[4:5], s[0:1], exec
109 ; FLAT-NEXT: s_and_b64 s[0:1], exec, s[4:5]
175 ; SI-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
176 ; SI-NEXT: s_and_b64 s[0:1], exec, s[4:5]
177 ; SI-NEXT: s_and_b64 s[2:3], exec, s[2:3]
180 ; SI-NEXT: s_and_b64 s[4:5], exec, s[4:5]
[all …]
Dimage-sample-waterfall.ll17 ; GCN-NEXT: s_and_b64 [[AND0:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
22 ; GCN-NEXT: s_and_b64 [[AND1:s\[[0-9]+:[0-9]+\]]], [[AND0]], [[CMP2]]
23 ; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[AND1]], [[CMP3]]
46 ; GCN-NEXT: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
17 ; The check for "s_and_b64 vcc, exec, something" checks that the bug is fixed.
21 ; CHECK: s_and_b64 vcc, exec,
Dllvm.amdgcn.image.sample.d16.dim.ll12 ; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
21 ; GFX81-NEXT: s_and_b64 exec, exec, s[12:13]
30 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
55 ; TONGA-NEXT: s_and_b64 exec, exec, s[14:15]
71 ; GFX81-NEXT: s_and_b64 exec, exec, s[14:15]
89 ; GFX9-NEXT: s_and_b64 exec, exec, s[14:15]
210 ; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
222 ; GFX81-NEXT: s_and_b64 exec, exec, s[12:13]
231 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
260 ; TONGA-NEXT: s_and_b64 exec, exec, s[12:13]
[all …]
Dmultilevel-break.ll55 ; GCN-NEXT: s_and_b64 s[2:3], exec, s[2:3]
69 ; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7]
88 ; GCN-NEXT: s_and_b64 s[10:11], vcc, exec
190 ; GCN-NEXT: s_and_b64 s[6:7], exec, s[6:7]
193 ; GCN-NEXT: s_and_b64 s[6:7], s[8:9], exec
203 ; GCN-NEXT: s_and_b64 vcc, exec, vcc
211 ; GCN-NEXT: s_and_b64 vcc, exec, vcc
226 ; GCN-NEXT: s_and_b64 vcc, exec, s[10:11]
231 ; GCN-NEXT: s_and_b64 vcc, exec, vcc
241 ; GCN-NEXT: s_and_b64 s[10:11], vcc, exec
Dllvm.amdgcn.image.sample.dim.ll11 ; VERDE-NEXT: s_and_b64 exec, exec, s[12:13]
20 ; GFX6789-NEXT: s_and_b64 exec, exec, s[12:13]
49 ; VERDE-NEXT: s_and_b64 exec, exec, s[14:15]
73 ; GFX6789-NEXT: s_and_b64 exec, exec, s[14:15]
117 ; VERDE-NEXT: s_and_b64 exec, exec, s[12:13]
129 ; GFX6789-NEXT: s_and_b64 exec, exec, s[12:13]
164 ; VERDE-NEXT: s_and_b64 exec, exec, s[12:13]
176 ; GFX6789-NEXT: s_and_b64 exec, exec, s[12:13]
211 ; VERDE-NEXT: s_and_b64 exec, exec, s[12:13]
223 ; GFX6789-NEXT: s_and_b64 exec, exec, s[12:13]
[all …]
Dsi-annotate-cfg-loop-assert.ll12 ; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]
15 ; CHECK-NEXT: s_and_b64 vcc, exec, 0
Dbranch-condition-and.ll7 ; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair
15 ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]]
Dbfi_int.ll126 ; GCN: s_and_b64
141 ; GCN: s_and_b64
155 ; GCN: s_and_b64
168 ; GCN: s_and_b64
170 ; GCN: s_and_b64
Dinfinite-loop.ll43 ; SI-NEXT: s_and_b64 vcc, exec, -1
85 ; SI-NEXT: s_and_b64 vcc, exec, -1
95 ; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
104 ; SI-NEXT: s_and_b64 vcc, exec, 0
153 ; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1]
Dloop_break.ll56 ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
60 ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
125 ; GCN-NEXT: s_and_b64 s[8:9], s[0:1], exec
135 ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
140 ; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7]
220 ; GCN-NEXT: s_and_b64 s[8:9], s[8:9], exec
230 ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
235 ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
318 ; GCN-NEXT: s_and_b64 s[8:9], vcc, exec
323 ; GCN-NEXT: s_and_b64 s[8:9], exec, s[4:5]
[all …]
Dwqm.ll22 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
45 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
67 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
97 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
424 ;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
425 ;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
462 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
466 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
510 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
575 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
[all …]
Delse.ll31 ; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
32 ; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
Dselect-opt.ll10 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
26 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
42 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
58 ; GCN: s_and_b64 vcc, vcc, [[CMP1]]
Dshift-i128.ll156 ; GCN-NEXT: s_and_b64 vcc, s[4:5], vcc
174 ; GCN-NEXT: s_and_b64 vcc, s[4:5], vcc
312 ; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
329 ; GCN-NEXT: s_and_b64 vcc, s[8:9], s[6:7]
361 ; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
378 ; GCN-NEXT: s_and_b64 vcc, s[8:9], s[6:7]
410 ; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
427 ; GCN-NEXT: s_and_b64 vcc, s[8:9], s[6:7]
461 ; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1]
484 ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
[all …]
Dllvm.amdgcn.image.gather4.a16.dim.ll12 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
39 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
66 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
93 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
120 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
149 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
176 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
203 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
232 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
262 ; GFX9-NEXT: s_and_b64 exec, exec, s[12:13]
Dptrmask.ll70 ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]
80 ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5]
92 ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
/external/llvm-project/llvm/test/MC/AMDGPU/
Dliterals.s549 s_and_b64 s[0:1], s[0:1], src_vccz label
553 s_and_b64 s[0:1], s[0:1], src_execz label
557 s_and_b64 s[0:1], s[0:1], src_scc label
679 s_and_b64 s[0:1], s[0:1], src_shared_base label
683 s_and_b64 s[0:1], s[0:1], src_shared_limit label
687 s_and_b64 s[0:1], s[0:1], src_private_base label
691 s_and_b64 s[0:1], s[0:1], src_private_limit label
695 s_and_b64 s[0:1], s[0:1], src_pops_exiting_wave_id label
Dsop2-err.s12 s_and_b64 s[2:3], 0x12345678, 0x12345679 label
Dsop2.s66 s_and_b64 null, s[4:5], s[6:7] label
71 s_and_b64 s[2:3], s[4:5], s[6:7] label
/external/llvm/test/CodeGen/AMDGPU/
Dwqm.ll40 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
62 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
122 ;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
123 ;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
158 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
162 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
208 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
284 ;CHECK: s_and_b64 exec, exec, [[ORIG]]
323 ; CHECK: s_and_b64 exec, exec, [[ORIG]]
346 ; CHECK: s_and_b64 exec, exec, [[ORIG]]
Dsmrd-vccz-bug.ll8 ; GCN: s_and_b64 vcc, exec, [[MASK]]
32 ; GCN: s_and_b64 vcc, exec, vcc
Duniform-cfg.ll35 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
92 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
123 ; SI: s_and_b64 vcc, exec, [[COND]]
148 ; SI: s_and_b64 vcc, exec, [[COND]]
257 ; SI: s_and_b64 vcc, exec, [[MASK]]
288 ; SI: s_and_b64 vcc, exec, vcc
Dand.ll164 ; SI: s_and_b64
193 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}
369 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
384 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
399 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
414 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
455 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
470 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_gfx10.txt6 # GFX10: s_and_b64 s[0:1], null, null ; encoding: [0x7d,0x7d,0x80,0x87]

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