| /external/llvm-project/llvm/test/MC/AMDGPU/ |
| D | branch-comment.s | 8 s_branch loop_start_nosym label
12 s_branch loop_end_nosym label
22 s_branch loop_start_sym label
26 s_branch loop_end_sym label
32 s_branch 65535 label
35 s_branch 32768 label
38 s_branch 32767 label
|
| D | sopp-err.s | 172 s_branch 0x80000000ffff label
175 s_branch 0x10000 label
178 s_branch -32769 label
181 s_branch 1.0 label
184 s_branch s0 label
187 s_branch offset:1 label
|
| D | labels-branch.s | 5 s_branch loop_start label
11 s_branch loop_end label
18 s_branch gds label
|
| D | sopp.s | 25 s_branch 2 label
391 s_branch 1+offset label
395 s_branch offset+1 label
|
| D | labels-branch-err.s | 4 s_branch undef_label label
|
| D | max-branch-distance.s | 7 s_branch LBB0_0
|
| D | gfx10_err_pos.s | 74 s_branch 0x10000 label
814 s_branch offset:1 label
1143 s_branch 1+x label
|
| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | gfx7_label.rst | 28 s_branch 32
29 s_branch offset + 2
30 s_branch label_1
31 s_branch label_2
32 s_branch label_3
33 s_branch label_4
|
| D | gfx9_label.rst | 28 s_branch 32
29 s_branch offset + 2
30 s_branch label_1
31 s_branch label_2
32 s_branch label_3
33 s_branch label_4
|
| D | gfx8_label.rst | 28 s_branch 32
29 s_branch offset + 2
30 s_branch label_1
31 s_branch label_2
32 s_branch label_3
33 s_branch label_4
|
| D | gfx10_label.rst | 28 s_branch 32
29 s_branch offset + 2
30 s_branch label_1
31 s_branch label_2
32 s_branch label_3
33 s_branch label_4
|
| /external/llvm/test/MC/AMDGPU/ |
| D | labels-branch.s | 4 s_branch loop_start label
8 s_branch loop_end label
13 s_branch gds label
|
| D | sopp.s | 25 s_branch 2 label
|
| /external/mesa3d/src/amd/compiler/tests/ |
| D | test_assembler.cpp | 50 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
73 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
141 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 0);
189 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 1);
193 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
212 bld.sopp(aco_opcode::s_branch, Definition(PhysReg(0), s2), 2);
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | cf-loop-on-constant.ll | 8 ; GCN: s_branch [[LABEL]]
33 ; GCN: s_branch [[LABEL]]
53 ; GCN-NOT: s_branch
75 ; GCN-NOT: s_branch
|
| D | infinite-loop.ll | 9 ; SI: s_branch BB0_1
|
| D | si-lower-control-flow-unreachable-block.ll | 7 ; GCN: s_branch BB0_1
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | control-flow-optnone.ll | 10 ; GCN: s_branch
20 ; GCN-NEXT: s_branch
|
| D | cf-loop-on-constant.ll | 34 ; GCN: s_branch [[LABEL]]
54 ; GCN-NOT: s_branch
76 ; GCN-NOT: s_branch
|
| D | i1-copy-from-loop.ll | 11 ; SI-NEXT: s_branch BB0_3
44 ; SI-NEXT: s_branch BB0_1
|
| D | multilevel-break.ll | 51 ; GCN-NEXT: s_branch BB0_2
65 ; GCN-NEXT: s_branch BB0_4
90 ; GCN-NEXT: s_branch BB0_3
187 ; GCN-NEXT: s_branch BB1_2
243 ; GCN-NEXT: s_branch BB1_1
|
| D | si-annotate-cf.ll | 182 ; SI-NEXT: s_branch BB3_4
215 ; SI-NEXT: s_branch BB3_1
254 ; FLAT-NEXT: s_branch BB3_4
287 ; FLAT-NEXT: s_branch BB3_1
|
| D | divergent-branch-uniform-condition.ll | 29 ; ISA-NEXT: s_branch BB0_3
58 ; ISA-NEXT: s_branch BB0_1
|
| D | vgpr-descriptor-waterfall-loop-idom-update.ll | 36 ; GCN-NEXT: s_branch BB0_1
|
| /external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/ |
| D | different-addrspace-crash.ll | 15 ;CHECK: s_branch [[LOOP_LABEL]]
|