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Searched refs:s_sext_i32_i8 (Results 1 – 25 of 38) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Didot4s.ll21 ; GFX7-NEXT: s_sext_i32_i8 s6, s4
22 ; GFX7-NEXT: s_sext_i32_i8 s7, s5
50 ; GFX8-NEXT: s_sext_i32_i8 s4, s2
51 ; GFX8-NEXT: s_sext_i32_i8 s5, s3
82 ; GFX9-NODL-NEXT: s_sext_i32_i8 s4, s2
83 ; GFX9-NODL-NEXT: s_sext_i32_i8 s5, s3
187 ; GFX7-NEXT: s_sext_i32_i8 s6, s4
188 ; GFX7-NEXT: s_sext_i32_i8 s7, s5
226 ; GFX8-NEXT: s_sext_i32_i8 s2, s0
227 ; GFX8-NEXT: s_sext_i32_i8 s3, s1
[all …]
Dsext-in-reg.ll27 ; GCN: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
63 ; GCN: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
338 ; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
339 ; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
355 ; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
356 ; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
357 ; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
358 ; GCN: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
621 ; SI: s_sext_i32_i8 [[SSEXT:s[0-9]+]], [[VAL]]
Dsint_to_fp.f64.ll75 ; SI: s_sext_i32_i8 [[SEXT:s[0-9]+]], [[VAL]]
Didot4u.ll1396 ; GFX7-NEXT: s_sext_i32_i8 s6, s4
1397 ; GFX7-NEXT: s_sext_i32_i8 s7, s5
1431 ; GFX8-NEXT: s_sext_i32_i8 s3, s1
1434 ; GFX8-NEXT: s_sext_i32_i8 s2, s0
1461 ; GFX9-NODL-NEXT: s_sext_i32_i8 s5, s3
1464 ; GFX9-NODL-NEXT: s_sext_i32_i8 s4, s2
1491 ; GFX9-DL-NEXT: s_sext_i32_i8 s5, s3
1494 ; GFX9-DL-NEXT: s_sext_i32_i8 s4, s2
1523 ; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0
1524 ; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1
Dsmed3.ll570 ; GCN: s_sext_i32_i8
571 ; GCN: s_sext_i32_i8
572 ; GCN: s_sext_i32_i8
Dmin.ll66 ; GCN: s_sext_i32_i8
67 ; GCN: s_sext_i32_i8
Dsign_extend.ll351 ; SI-NEXT: s_sext_i32_i8 s0, s0
375 ; VI-NEXT: s_sext_i32_i8 s0, s0
Dmad_uint24.ll58 ; GCN2: s_sext_i32_i8 s0, [[MAD]]
Dload-constant-i8.ll226 ; GCN-DAG: s_sext_i32_i8
277 ; GCN-DAG: s_sext_i32_i8
Dllvm.amdgcn.sbfe.ll458 ; GCN: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}}
Dkernel-args.ll59 ; HSA-GFX9: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]]
/external/llvm/test/CodeGen/AMDGPU/
Dsext-in-reg.ll26 ; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
62 ; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]]
315 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
316 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
332 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
333 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
334 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
335 ; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}}
487 ; SI: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}}
Dsmed3.ll381 ; GCN: s_sext_i32_i8
382 ; GCN: s_sext_i32_i8
383 ; GCN: s_sext_i32_i8
Dsign_extend.ll67 ; GCN-DAG: s_sext_i32_i8 [[EXT0:s[0-9]+]], [[VAL]]
Dmin.ll61 ; SI: s_sext_i32_i8
62 ; SI: s_sext_i32_i8
Dload-constant-i8.ll196 ; GCN-DAG: s_sext_i32_i8
232 ; GCN-DAG: s_sext_i32_i8
/external/llvm/test/MC/AMDGPU/
Dsop1.s139 s_sext_i32_i8 s1, s2 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dsop1.s181 s_sext_i32_i8 s1, s2 label
Dgfx7_asm_all.s12372 s_sext_i32_i8 s5, s1 label
12375 s_sext_i32_i8 s103, s1 label
12378 s_sext_i32_i8 flat_scratch_lo, s1 label
12381 s_sext_i32_i8 flat_scratch_hi, s1 label
12384 s_sext_i32_i8 vcc_lo, s1 label
12387 s_sext_i32_i8 vcc_hi, s1 label
12390 s_sext_i32_i8 tba_lo, s1 label
12393 s_sext_i32_i8 tba_hi, s1 label
12396 s_sext_i32_i8 tma_lo, s1 label
12399 s_sext_i32_i8 tma_hi, s1 label
[all …]
Dgfx8_asm_all.s13147 s_sext_i32_i8 s5, s1 label
13150 s_sext_i32_i8 s101, s1 label
13153 s_sext_i32_i8 flat_scratch_lo, s1 label
13156 s_sext_i32_i8 flat_scratch_hi, s1 label
13159 s_sext_i32_i8 vcc_lo, s1 label
13162 s_sext_i32_i8 vcc_hi, s1 label
13165 s_sext_i32_i8 tba_lo, s1 label
13168 s_sext_i32_i8 tba_hi, s1 label
13171 s_sext_i32_i8 tma_lo, s1 label
13174 s_sext_i32_i8 tma_hi, s1 label
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dashr.ll60 ; GFX6-NEXT: s_sext_i32_i8 s0, s0
66 ; GFX8-NEXT: s_sext_i32_i8 s0, s0
67 ; GFX8-NEXT: s_sext_i32_i8 s1, s1
73 ; GFX9-NEXT: s_sext_i32_i8 s0, s0
74 ; GFX9-NEXT: s_sext_i32_i8 s1, s1
84 ; GCN-NEXT: s_sext_i32_i8 s0, s0
Dllvm.amdgcn.sbfe.ll832 ; GFX6-NEXT: s_sext_i32_i8 s0, s0
855 ; GFX6-NEXT: s_sext_i32_i8 s0, s0
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt96 # VI: s_sext_i32_i8 s1, s2 ; encoding: [0x02,0x16,0x81,0xbe]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt105 # VI: s_sext_i32_i8 s1, s2 ; encoding: [0x02,0x16,0x81,0xbe]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td217 def S_SEXT_I32_I8 : SOP1_32 <"s_sext_i32_i8",

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