Searched refs:sabd (Results 1 – 25 of 52) sorted by relevance
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10 sabd z31.b, p7/m, z31.b, z31.b label16 sabd z31.h, p7/m, z31.h, z31.h label22 sabd z31.s, p7/m, z31.s, z31.s label28 sabd z31.d, p7/m, z31.d, z31.d label44 sabd z4.d, p7/m, z4.d, z31.d label56 sabd z4.d, p7/m, z4.d, z31.d label
3 sabd z0.b, p8/m, z0.b, z0.b label
4 declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>)23 %abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)24 ; CHECK: sabd v0.8b, v0.8b, v1.8b30 %abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)37 declare <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8>, <16 x i8>)56 %abd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)57 ; CHECK: sabd v0.16b, v0.16b, v1.16b63 %abd = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)70 declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>)89 %abd = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)[all …]
9 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)19 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)29 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)41 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)53 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)65 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)236 ;CHECK: sabd.8b239 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)245 ;CHECK: sabd.16b248 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)[all …]
35 declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>)37 declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>)39 declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>)1077 %vabd.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %a, <8 x i8> %b)1086 %vabd2.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %a, <4 x i16> %b)1095 %vabd2.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %a, <2 x i32> %b)1131 %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %b, <8 x i8> %c)1141 %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %b, <4 x i16> %c)1151 %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %b, <2 x i32> %c)1193 …%vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %shuffle.i.i, <8 x i8> %shu…[all …]
11 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)22 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)33 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)45 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)57 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)69 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)177 ; CHECK: sabd.16b209 ; CHECK: sabd.8h256 ; CHECK: sabd.4s350 ;CHECK: sabd.8b[all …]
289 ; CHECK: sabd z0.b, p0/m, z0.b, z1.b291 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1> %pg,299 ; CHECK: sabd z0.h, p0/m, z0.h, z1.h301 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1> %pg,309 ; CHECK: sabd z0.s, p0/m, z0.s, z1.s311 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> %pg,319 ; CHECK: sabd z0.d, p0/m, z0.d, z1.d321 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.nxv2i64(<vscale x 2 x i1> %pg,402 declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>,…403 declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>,…[all …]
20 0x20,0x74,0x22,0x0e = sabd v0.8b, v1.8b, v2.8b21 0x20,0x74,0x22,0x4e = sabd v0.16b, v1.16b, v2.16b22 0x20,0x74,0x62,0x0e = sabd v0.4h, v1.4h, v2.4h23 0x20,0x74,0x62,0x4e = sabd v0.8h, v1.8h, v2.8h24 0x20,0x74,0xa2,0x0e = sabd v0.2s, v1.2s, v2.2s25 0x20,0x74,0xa2,0x4e = sabd v0.4s, v1.4s, v2.4s
54 sabd v0.8b, v1.8b, v2.8b55 sabd v0.16b, v1.16b, v2.16b56 sabd v0.4h, v1.4h, v2.4h57 sabd v0.8h, v1.8h, v2.8h58 sabd v0.2s, v1.2s, v2.2s59 sabd v0.4s, v1.4s, v2.4s
339 sabd.8b v0, v0, v0410 ; CHECK: sabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x0e]
1364 __ sabd(v0.V16B(), v15.V16B(), v13.V16B()); in GenerateTestSequenceNEON() local1365 __ sabd(v15.V2S(), v7.V2S(), v30.V2S()); in GenerateTestSequenceNEON() local1366 __ sabd(v17.V4H(), v17.V4H(), v12.V4H()); in GenerateTestSequenceNEON() local1367 __ sabd(v7.V4S(), v4.V4S(), v22.V4S()); in GenerateTestSequenceNEON() local1368 __ sabd(v23.V8B(), v3.V8B(), v26.V8B()); in GenerateTestSequenceNEON() local1369 __ sabd(v20.V8H(), v28.V8H(), v5.V8H()); in GenerateTestSequenceNEON() local
206 __ sabd(z2.VnD(), p2.Merging(), z2.VnD(), z2.VnD()); in TEST() local761 __ sabd(z1.VnB(), p3.Merging(), z1.VnB(), z15.VnB()); in TEST() local1459 __ sabd(z28.VnS(), p7.Merging(), z28.VnS(), z11.VnS()); in TEST() local
1589 TEST_NEON(sabd_0, sabd(v0.V8B(), v1.V8B(), v2.V8B()))1590 TEST_NEON(sabd_1, sabd(v0.V16B(), v1.V16B(), v2.V16B()))1591 TEST_NEON(sabd_2, sabd(v0.V4H(), v1.V4H(), v2.V4H()))1592 TEST_NEON(sabd_3, sabd(v0.V8H(), v1.V8H(), v2.V8H()))1593 TEST_NEON(sabd_4, sabd(v0.V2S(), v1.V2S(), v2.V2S()))1594 TEST_NEON(sabd_5, sabd(v0.V4S(), v1.V4S(), v2.V4S()))
2201 COMPARE_PREFIX(sabd(z11.VnB(), p6.Merging(), z11.VnB(), z31.VnB()), in TEST()2203 COMPARE_PREFIX(sabd(z11.VnH(), p6.Merging(), z11.VnH(), z31.VnH()), in TEST()2205 COMPARE_PREFIX(sabd(z11.VnS(), p6.Merging(), z11.VnS(), z31.VnS()), in TEST()2207 COMPARE_PREFIX(sabd(z11.VnD(), p6.Merging(), z11.VnD(), z31.VnD()), in TEST()
1128 0x~~~~~~~~~~~~~~~~ 4e2d75e0 sabd v0.16b, v15.16b, v13.16b1129 0x~~~~~~~~~~~~~~~~ 0ebe74ef sabd v15.2s, v7.2s, v30.2s1130 0x~~~~~~~~~~~~~~~~ 0e6c7631 sabd v17.4h, v17.4h, v12.4h1131 0x~~~~~~~~~~~~~~~~ 4eb67487 sabd v7.4s, v4.4s, v22.4s1132 0x~~~~~~~~~~~~~~~~ 0e3a7477 sabd v23.8b, v3.8b, v26.8b1133 0x~~~~~~~~~~~~~~~~ 4e657794 sabd v20.8h, v28.8h, v5.8h
1127 0x~~~~~~~~~~~~~~~~ 4e2d75e0 sabd v0.16b, v15.16b, v13.16b ### {NEON} ###1128 0x~~~~~~~~~~~~~~~~ 0ebe74ef sabd v15.2s, v7.2s, v30.2s ### {NEON} ###1129 0x~~~~~~~~~~~~~~~~ 0e6c7631 sabd v17.4h, v17.4h, v12.4h ### {NEON} ###1130 0x~~~~~~~~~~~~~~~~ 4eb67487 sabd v7.4s, v4.4s, v22.4s ### {NEON} ###1131 0x~~~~~~~~~~~~~~~~ 0e3a7477 sabd v23.8b, v3.8b, v26.8b ### {NEON} ###1132 0x~~~~~~~~~~~~~~~~ 4e657794 sabd v20.8h, v28.8h, v5.8h ### {NEON} ###
1127 0x~~~~~~~~~~~~~~~~ 4e2d75e0 sabd v0.16b, v15.16b, v13.16b [1;35mNEON[0;m1128 0x~~~~~~~~~~~~~~~~ 0ebe74ef sabd v15.2s, v7.2s, v30.2s [1;35mNEON[0;m1129 0x~~~~~~~~~~~~~~~~ 0e6c7631 sabd v17.4h, v17.4h, v12.4h [1;35mNEON[0;m1130 0x~~~~~~~~~~~~~~~~ 4eb67487 sabd v7.4s, v4.4s, v22.4s [1;35mNEON[0;m1131 0x~~~~~~~~~~~~~~~~ 0e3a7477 sabd v23.8b, v3.8b, v26.8b [1;35mNEON[0;m1132 0x~~~~~~~~~~~~~~~~ 4e657794 sabd v20.8h, v28.8h, v5.8h [1;35mNEON[0;m
1127 0x~~~~~~~~~~~~~~~~ 4e2d75e0 sabd v0.16b, v15.16b, v13.16b // Needs: NEON1128 0x~~~~~~~~~~~~~~~~ 0ebe74ef sabd v15.2s, v7.2s, v30.2s // Needs: NEON1129 0x~~~~~~~~~~~~~~~~ 0e6c7631 sabd v17.4h, v17.4h, v12.4h // Needs: NEON1130 0x~~~~~~~~~~~~~~~~ 4eb67487 sabd v7.4s, v4.4s, v22.4s // Needs: NEON1131 0x~~~~~~~~~~~~~~~~ 0e3a7477 sabd v23.8b, v3.8b, v26.8b // Needs: NEON1132 0x~~~~~~~~~~~~~~~~ 4e657794 sabd v20.8h, v28.8h, v5.8h // Needs: NEON
4753 { /* AArch64_SABDv16i8, ARM64_INS_SABD: sabd.16b $rd, $rn, $rm| */4757 { /* AArch64_SABDv2i32, ARM64_INS_SABD: sabd.2s $rd, $rn, $rm| */4761 { /* AArch64_SABDv4i16, ARM64_INS_SABD: sabd.4h $rd, $rn, $rm| */4765 { /* AArch64_SABDv4i32, ARM64_INS_SABD: sabd.4s $rd, $rn, $rm| */4769 { /* AArch64_SABDv8i16, ARM64_INS_SABD: sabd.8h $rd, $rn, $rm| */4773 { /* AArch64_SABDv8i8, ARM64_INS_SABD: sabd.8b $rd, $rn, $rm| */
2458 void sabd(const VRegister& vd, const VRegister& vn, const VRegister& vm);5186 void sabd(const ZRegister& zd,