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Searched refs:saddlv (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/test/Transforms/SLPVectorizer/AArch64/
Dmismatched-intrinsics.ll7 ; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v4i32
8 ; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v2i32
10 %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2
11 %vaddlv_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in2) #2
17 declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1)
18 declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in1)
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/AArch64/
Dmismatched-intrinsics.ll8 ; CHECK-NEXT: [[VADDLVQ_S32_I:%.*]] = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> …
9 ; CHECK-NEXT: [[VADDLV_S32_I:%.*]] = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> […
15 %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2
16 %vaddlv_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in2) #2
22 declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1)
23 declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in1)
/external/capstone/suite/MC/AArch64/
Dneon-across.s.cs2 0x20,0x38,0x30,0x0e = saddlv h0, v1.8b
3 0x20,0x38,0x30,0x4e = saddlv h0, v1.16b
4 0x20,0x38,0x70,0x0e = saddlv s0, v1.4h
5 0x20,0x38,0x70,0x4e = saddlv s0, v1.8h
6 0x20,0x38,0xb0,0x4e = saddlv d0, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-across.s9 saddlv h0, v1.8b
10 saddlv h0, v1.16b
11 saddlv s0, v1.4h
12 saddlv s0, v1.8h
13 saddlv d0, v1.4s define
Dneon-diagnostics.s3713 saddlv b0, v1.8b
3714 saddlv b0, v1.16b
3715 saddlv h0, v1.4h
3716 saddlv h0, v1.8h
3717 saddlv s0, v1.2s
3718 saddlv s0, v1.4s
3719 saddlv d0, v1.2s define
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-across.s9 saddlv h0, v1.8b
10 saddlv h0, v1.16b
11 saddlv s0, v1.4h
12 saddlv s0, v1.8h
13 saddlv d0, v1.4s define
Dneon-diagnostics.s3653 saddlv b0, v1.8b
3654 saddlv b0, v1.16b
3655 saddlv h0, v1.4h
3656 saddlv h0, v1.8h
3657 saddlv s0, v1.2s
3658 saddlv s0, v1.4s
3659 saddlv d0, v1.2s define
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-across.ll67 declare i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32>)
69 declare i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16>)
71 declare i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8>)
77 declare i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16>)
79 declare i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8>)
83 ; CHECK: saddlv h{{[0-9]+}}, {{v[0-9]+}}.8b
85 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %a)
92 ; CHECK: saddlv s{{[0-9]+}}, {{v[0-9]+}}.4h
94 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a)
117 ; CHECK: saddlv h{{[0-9]+}}, {{v[0-9]+}}.16b
[all …]
Darm64-vaddlv.ll9 %vaddlv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
25 declare i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32>) nounwind readnone
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-neon-across.ll67 declare i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32>)
69 declare i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16>)
71 declare i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8>)
77 declare i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16>)
79 declare i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8>)
83 ; CHECK: saddlv h{{[0-9]+}}, {{v[0-9]+}}.8b
85 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %a)
92 ; CHECK: saddlv s{{[0-9]+}}, {{v[0-9]+}}.4h
94 %saddlvv.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a)
117 ; CHECK: saddlv h{{[0-9]+}}, {{v[0-9]+}}.16b
[all …]
Darm64-vaddlv.ll9 %vaddlv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
25 declare i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32>) nounwind readnone
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1394 __ saddlv(d12, v7.V4S()); in GenerateTestSequenceNEON() local
1395 __ saddlv(h14, v28.V16B()); in GenerateTestSequenceNEON() local
1396 __ saddlv(h30, v30.V8B()); in GenerateTestSequenceNEON() local
1397 __ saddlv(s27, v3.V4H()); in GenerateTestSequenceNEON() local
1398 __ saddlv(s16, v16.V8H()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc1607 TEST_NEON(saddlv_0, saddlv(h0, v1.V8B()))
1608 TEST_NEON(saddlv_1, saddlv(h0, v1.V16B()))
1609 TEST_NEON(saddlv_2, saddlv(s0, v1.V4H()))
1610 TEST_NEON(saddlv_3, saddlv(s0, v1.V8H()))
1611 TEST_NEON(saddlv_4, saddlv(d0, v1.V4S()))
Dtest-simulator-aarch64.cc4902 DEFINE_TEST_NEON_ACROSS_LONG(saddlv, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1158 0x~~~~~~~~~~~~~~~~ 4eb038ec saddlv d12, v7.4s
1159 0x~~~~~~~~~~~~~~~~ 4e303b8e saddlv h14, v28.16b
1160 0x~~~~~~~~~~~~~~~~ 0e303bde saddlv h30, v30.8b
1161 0x~~~~~~~~~~~~~~~~ 0e70387b saddlv s27, v3.4h
1162 0x~~~~~~~~~~~~~~~~ 4e703a10 saddlv s16, v16.8h
Dlog-disasm1158 0x~~~~~~~~~~~~~~~~ 4eb038ec saddlv d12, v7.4s
1159 0x~~~~~~~~~~~~~~~~ 4e303b8e saddlv h14, v28.16b
1160 0x~~~~~~~~~~~~~~~~ 0e303bde saddlv h30, v30.8b
1161 0x~~~~~~~~~~~~~~~~ 0e70387b saddlv s27, v3.4h
1162 0x~~~~~~~~~~~~~~~~ 4e703a10 saddlv s16, v16.8h
Dlog-cpufeatures-custom1157 0x~~~~~~~~~~~~~~~~ 4eb038ec saddlv d12, v7.4s ### {NEON} ###
1158 0x~~~~~~~~~~~~~~~~ 4e303b8e saddlv h14, v28.16b ### {NEON} ###
1159 0x~~~~~~~~~~~~~~~~ 0e303bde saddlv h30, v30.8b ### {NEON} ###
1160 0x~~~~~~~~~~~~~~~~ 0e70387b saddlv s27, v3.4h ### {NEON} ###
1161 0x~~~~~~~~~~~~~~~~ 4e703a10 saddlv s16, v16.8h ### {NEON} ###
Dlog-cpufeatures-colour1157 0x~~~~~~~~~~~~~~~~ 4eb038ec saddlv d12, v7.4s NEON
1158 0x~~~~~~~~~~~~~~~~ 4e303b8e saddlv h14, v28.16b NEON
1159 0x~~~~~~~~~~~~~~~~ 0e303bde saddlv h30, v30.8b NEON
1160 0x~~~~~~~~~~~~~~~~ 0e70387b saddlv s27, v3.4h NEON
1161 0x~~~~~~~~~~~~~~~~ 4e703a10 saddlv s16, v16.8h NEON
Dlog-cpufeatures1157 0x~~~~~~~~~~~~~~~~ 4eb038ec saddlv d12, v7.4s // Needs: NEON
1158 0x~~~~~~~~~~~~~~~~ 4e303b8e saddlv h14, v28.16b // Needs: NEON
1159 0x~~~~~~~~~~~~~~~~ 0e303bde saddlv h30, v30.8b // Needs: NEON
1160 0x~~~~~~~~~~~~~~~~ 0e70387b saddlv s27, v3.4h // Needs: NEON
1161 0x~~~~~~~~~~~~~~~~ 4e703a10 saddlv s16, v16.8h // Needs: NEON
Dlog-all5296 0x~~~~~~~~~~~~~~~~ 4eb038ec saddlv d12, v7.4s
5298 0x~~~~~~~~~~~~~~~~ 4e303b8e saddlv h14, v28.16b
5300 0x~~~~~~~~~~~~~~~~ 0e303bde saddlv h30, v30.8b
5302 0x~~~~~~~~~~~~~~~~ 0e70387b saddlv s27, v3.4h
5304 0x~~~~~~~~~~~~~~~~ 4e703a10 saddlv s16, v16.8h
/external/capstone/arch/AArch64/
DAArch64MappingInsnOp.inc4825 { /* AArch64_SADDLVv16i8v, ARM64_INS_SADDLV: saddlv.16b $rd, $rn */
4829 { /* AArch64_SADDLVv4i16v, ARM64_INS_SADDLV: saddlv.4h $rd, $rn */
4833 { /* AArch64_SADDLVv4i32v, ARM64_INS_SADDLV: saddlv.4s $rd, $rn */
4837 { /* AArch64_SADDLVv8i16v, ARM64_INS_SADDLV: saddlv.8h $rd, $rn */
4841 { /* AArch64_SADDLVv8i8v, ARM64_INS_SADDLV: saddlv.8b $rd, $rn */
/external/vixl/src/aarch64/
Dsimulator-aarch64.h3452 LogicVRegister saddlv(VectorFormat vform,
Dassembler-aarch64.h3013 void saddlv(const VRegister& vd, const VRegister& vn);
Dlogic-aarch64.cc1455 LogicVRegister Simulator::saddlv(VectorFormat vform, in saddlv() function in vixl::aarch64::Simulator
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md4762 void saddlv(const VRegister& vd, const VRegister& vn)

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